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公开(公告)号：US20170123872A1
公开(公告)日：2017-05-04
申请号：US14925131
申请日：2015-10-28
Applicant: Intel Corporation
Inventor： Theodros Yigzaw , Mohan J. Kumar , Hisham Shafi , Ron Gabor , Ashok Raj
CPC classification number: G06F11/079 , G06F9/3004 , G06F9/30101 , G06F9/3016 , G06F11/0721 , G06F11/0784 , G06F11/0787 , G06F11/0793 , G06F12/00 , G06F12/0246
Abstract: In one embodiment, a processor includes a core having a fetch unit to fetch instructions, a decode unit to decode the instructions, and one or more execution units to execute the instructions. The core may further include: a first pair of block address range registers to store a start location and an end location of a block range within a non-volatile block storage coupled to the processor; and a block status storage to store an error indicator responsive to an occurrence of an error within the block range during a block operation. Other embodiments are described and claimed.
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12.发明申请CLEARING POISON STATUS ON READ ACCESSES TO VOLATILE MEMORY REGIONS ALLOCATED IN NON-VOLATILE MEMORY 有权在非易失性存储器中分配的易失性存储器区域读取访问的清除毒液状态公开(公告)号：US20170068537A1
公开(公告)日：2017-03-09
申请号：US14845503
申请日：2015-09-04
Applicant: Intel Corporation
Inventor： Raj K. Ramanujan , Camille C. Raad , Richard P. Mangold , Theodros Yigzaw
CPC classification number: G06F11/3037 , G06F11/073 , G06F11/0793 , G06F11/1612 , G06F11/167 , G06F12/00 , G11C29/42 , G11C29/52 , G11C2029/0411
Abstract: Systems and methods may provide for detecting that a read operation is directed to a memory region while the memory region is in a poisoned state and clearing the poisoned state if volatile data stored in the memory region does not correspond to a known data pattern. Additionally, the memory region may be maintained in the poisoned state if the volatile data stored in the memory region corresponds to the known data pattern. In one example, an error may be detected, wherein the error is associated with a write operation directed to the memory region. In such a case, the poisoned state may be set for the volatile data in response to the error and the known data pattern may be written to the memory region.
Abstract translation: 如果存储在存储器区域中的易失性数据不对应于已知的数据模式，则系统和方法可以提供用于检测在存储器区域处于中毒状态时读取操作被引导到存储器区域并清除中毒状态。 此外，如果存储在存储器区域中的易失性数据对应于已知数据模式，则存储器区域可以被维持在中毒状态。 在一个示例中，可以检测到错误，其中错误与针对存储器区域的写入操作相关联。 在这种情况下，响应于错误可以为易失性数据设置中毒状态，并且可以将已知数据模式写入存储器区域。
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公开(公告)号：US10319458B2
公开(公告)日：2019-06-11
申请号：US15457326
申请日：2017-03-13
Applicant: Intel Corporation
Inventor： Ashok Raj , Ron Gabor , Hisham Shafi , Mohan J. Kumar , Theodros Yigzaw
Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.
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公开(公告)号：US10296416B2
公开(公告)日：2019-05-21
申请号：US15201438
申请日：2016-07-02
Applicant: Intel Corporation
Inventor： Ashok Raj , Ron Gabor , Hisham Shafi , Sergiu Ghetie , Mohan J. Kumar , Theodros Yigzaw , Sarathy Jayakumar , Neeraj S. Upasani
Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
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公开(公告)号：US10162761B2
公开(公告)日：2018-12-25
申请号：US15465560
申请日：2017-03-21
Applicant: Intel Corporation
Inventor： Ashok Raj , Sreenivas Mandava , Sarathy Jayakumar , Mohan J Kumar , Theodros Yigzaw , Ronald N Story
IPC: G06F12/02 , G06F12/06 , G06F12/1009 , G06F9/26 , G06F9/30 , G06F13/24 , G06F13/364
Abstract: An apparatus and method are described for system physical address to memory module address translation. For example, one embodiment of an apparatus comprises: a fetch circuit of a core to fetch a system physical address (SPA) translate instruction from memory; a decode circuit of the core to decode the SPA translate instruction; a first register to store an SPA associated with the SPA translate instruction; a memory controller comprising one or more channel controllers to initiate a translation using the SPA, the memory controller to transmit a translation request to a first channel controller; the first channel controller to synthesize a response including dual in-line memory module (DIMM) address information; and a second register to store the DIMM address information to be used to identify the DIMM during subsequent memory transactions.
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Patent Agency Ranking
公开(公告)号：US09904586B2
公开(公告)日：2018-02-27
申请号：US14925131
申请日：2015-10-28
Applicant: Intel Corporation
Inventor： Theodros Yigzaw , Mohan J. Kumar , Hisham Shafi , Ron Gabor , Ashok Raj
CPC classification number: G06F11/079 , G06F9/3004 , G06F9/30101 , G06F9/3016 , G06F11/0721 , G06F11/0784 , G06F11/0787 , G06F11/0793 , G06F12/00 , G06F12/0246
Abstract: In one embodiment, a processor includes a core having a fetch unit to fetch instructions, a decode unit to decode the instructions, and one or more execution units to execute the instructions. The core may further include: a first pair of block address range registers to store a start location and an end location of a block range within a non-volatile block storage coupled to the processor; and a block status storage to store an error indicator responsive to an occurrence of an error within the block range during a block operation. Other embodiments are described and claimed.
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公开(公告)号：US09842015B2
公开(公告)日：2017-12-12
申请号：US14040092
申请日：2013-09-27
Applicant: INTEL CORPORATION
Inventor： Ashok Raj , Mohan J. Kumar , Jose A. Vargas , William G. Auld , Cameron B. McNairy , Theodros Yigzaw , James B. Crossland , Anthony E. Luck
CPC classification number: G06F11/0772 , G06F11/0712 , G06F11/0724 , G06F11/0784 , G06F11/0793
Abstract: A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.
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公开(公告)号：US09690640B2
公开(公告)日：2017-06-27
申请号：US14038334
申请日：2013-09-26
Applicant: Intel Corporation
Inventor： Raanan Sade , Ron Gabor , Deep K. Buch , Theodros Yigzaw , Stanislav Shwartsman
CPC classification number: G06F11/073 , G06F11/0793 , G06F11/08
Abstract: Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.
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19.发明授权Hardware apparatuses and methods to check data storage devices for transient faults 有权用于检查瞬态故障的数据存储设备的硬件设备和方法公开(公告)号：US09595349B2
公开(公告)日：2017-03-14
申请号：US14751113
申请日：2015-06-25
Applicant: Intel Corporation
Inventor： Ashok Raj , Ron Gabor , Hisham Shafi , Mohan J. Kumar , Theodros Yigzaw
CPC classification number: G11C29/38 , G11C13/0004 , G11C29/04 , G11C29/44 , G11C29/52 , G11C2029/0401
Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.
Abstract translation: 描述与硬件存储器测试单元相关的方法和装置，用于在将数据存储在数据存储设备的部分中和/或从数据存储设备的部分加载之前检查用于瞬态故障的数据存储设备的一部分。 在一个实施例中，集成电路包括用于对数据存储设备的一部分中的数据进行操作的硬件处理器，以及存储器测试单元，用于在将数据存储在该部分中之前检查数据存储设备中的瞬态故障的部分 的数据存储设备，其中如果由硬件处理器访问，则瞬态故障将导致机器检查异常。
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20.发明申请HARDWARE APPARATUSES AND METHODS TO CHECK DATA STORAGE DEVICES FOR TRANSIENT FAULTS 有权硬件设备和检查瞬时故障的数据存储设备的方法公开(公告)号：US20160379721A1
公开(公告)日：2016-12-29
申请号：US14751113
申请日：2015-06-25
Applicant: Intel Corporation
Inventor： Ashok Raj , Ron Gabor , Hisham Shafi , Mohan J. Kumar , Theodros Yigzaw
CPC classification number: G11C29/38 , G11C13/0004 , G11C29/04 , G11C29/44 , G11C29/52 , G11C2029/0401
Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.
Abstract translation: 描述与硬件存储器测试单元相关的方法和装置，用于在将数据存储在数据存储设备的部分中和/或从数据存储设备的部分加载之前检查用于瞬态故障的数据存储设备的一部分。 在一个实施例中，集成电路包括用于对数据存储设备的一部分中的数据进行操作的硬件处理器，以及存储器测试单元，用于在将数据存储在该部分中之前检查数据存储设备中的瞬态故障的部分 的数据存储设备，其中如果由硬件处理器访问，则瞬态故障将导致机器检查异常。
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