公开(公告)号：US20230086881A1

公开(公告)日：2023-03-23

申请号：US17481247

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Whitney BRYKS ,  Jieying KONG ,  Bainye Francoise ANGOUA ,  Junxin WANG ,  Sarah BLYTHE ,  Ala OMER ,  Dilan SENEVIRATNE

IPC: G02B6/43 ,  G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a double-sided glass substrate, to which a PIC is hybrid bonded to a first side of the glass substrate. A die is coupled with the second side of the glass substrate opposite the first side, the PIC and the die are electrically coupled with electrically conductive through glass vias that extend from the first side of the glass substrate to the second side of the glass substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20240186263A1

公开(公告)日：2024-06-06

申请号：US18060574

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Hong Seung YEON ,  Liang HE ,  Whitney BRYKS ,  Jung Kyu HAN ,  Gang DUAN

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/13 ,  H01L2224/32225 ,  H01L2924/3511

Abstract: The present disclosure is directed to a semiconductor carrier platform having a support panel with a top surface and a bottom surface, with the top surface providing a working surface for assembling IC packages using panel-level packaging technology. In an aspect, a backside molding layer may be positioned on the bottom surface of the support panel to prevent or correct any panel warpage. In another aspect, a removable film may be positioned between the bottom surface of the support panel and the backside molding layer to allow the support panel to be readily cleaned and reused.

公开(公告)号：US20240186197A1

公开(公告)日：2024-06-06

申请号：US18060592

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Aaditya Anand CANDADAI ,  Nicholas HAEHN ,  Ao WANG ,  Whitney BRYKS ,  Srinivas PIETAMBARAM

IPC: H01L23/16

CPC classification number: H01L23/16

Abstract: The present disclosure is directed to a semiconductor panel providing a laminated structure and a plurality of electrically isolated structures distributed throughout the laminated structure to increase an attraction between the laminated structure and an electrostatic chuck. In an aspect, the electrically isolated structures are positioned in spaces in the semiconductor panel without electrically active devices and interconnects. In yet another aspect, the present method provides a semiconductor panel and forming a plurality of electrically isolated structures in selected positions on the semiconductor panel and an electrostatic chuck configured to carry an electrostatic charge for producing an electrostatic force at its top surface, placing the semiconductor panel on the electrostatic chuck, and activating the electrostatic chuck to induce polarization at the top surface to produce an attractive force having a greater magnitude at the positions with the plurality of electrically isolated structures.

公开(公告)号：US20240178157A1

公开(公告)日：2024-05-30

申请号：US18071257

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Vinith BEJUGAM ,  Whitney BRYKS ,  Brandon C. MARIN ,  Vishal Bhimrao ZADE ,  Deniz TURAN ,  Srinivas V. PIETAMBARAM

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49822

Abstract: Embodiments disclosed herein include package substrates. In a particular embodiment, the package substrate comprises a core. The core may be a glass core. In an embodiment, buildup layers are provided over the core, and a shape memory polymer (SMP) is provided over the core.

公开(公告)号：US20240123561A1

公开(公告)日：2024-04-18

申请号：US17966021

申请日：2022-10-14

Applicant: Intel Corporation

Inventor： Yosef KORNBLUTH ,  Whitney BRYKS ,  Ravindranadh Tagore ELURI

IPC: B24B1/00 ,  B24B37/04 ,  B24B57/02

CPC classification number: B24B1/005 ,  B24B37/042 ,  B24B57/02

Abstract: This disclosure describes systems, methods, and devices related to enhanced plate polishing. A device may place a liquid between a plate and a wafer. The device may utilize a controller to vary a current flowing through an array of coils. The device may apply pressure on the plate to press against the liquid and the wafer.

公开(公告)号：US20240105476A1

公开(公告)日：2024-03-28

申请号：US17951114

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Whitney BRYKS ,  Thomas HEATON ,  Joshua STACEY ,  Dilan SENEVIRATNE ,  Cansu ERGENE

IPC: B05C13/02 ,  B05C5/02 ,  B05D1/26

CPC classification number: B05C13/02 ,  B05C5/02 ,  B05D1/26

Abstract: The present disclosure is directed to a coating module including: a coating stage and a plurality of vertical guides configured to perpendicularly extend from the coating stage; a vertical movement mechanism configured to lower a framed panel along the plurality of vertical guides onto the coating stage; an optical alignment tool configured to provide feedback on a lateral alignment between an edge of the coating stage and the framed panel; and a dispensing unit configured to coat a surface of the panel.

公开(公告)号：US20230090863A1

公开(公告)日：2023-03-23

申请号：US17482384

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Dilan SENEVIRATNE ,  Whitney BRYKS ,  Ala OMER ,  Jieying KONG ,  Sarah BLYTHE ,  Bainye Francoise ANGOUA

IPC: G02B6/42 ,  G02B6/12

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to dense integration of PICs in a substrate using an optical fanout structure that includes waveguides formed within a substrate to optically couple with the PICs at an edge of the substrate. One or more PICs may then be electrically with dies such as processor dies or memory dies. The one or more PICs may be located within a cavity in the substrate. The substrate may be made of glass or silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006203A1

公开(公告)日：2020-01-02

申请号：US16020122

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Brandon MARIN ,  Whitney BRYKS

IPC: H01L23/492 ,  H01L23/498

Abstract: A package substrate may include a build-up layer. The build-up layer may include a dielectric material and one or more microspheres. The one or more microspheres may include a magnetic core that includes a first material that is a first oxidation-resistant material. Further, the one or more microspheres may include a shell to encapsulate the core, and the shell may include a second material that is a second oxidation-resistant material. The package substrate may further include a metal layer coupled with the build-up layer.