公开(公告)号：US09921961B2

公开(公告)日：2018-03-20

申请号：US15400122

申请日：2017-01-06

Applicant: Intel Corporation

Inventor： Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Zhe Wang ,  Zeshan A. Chishti

IPC: G11C16/04 ,  G06F12/0804 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/0292 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/502 ,  G06F2212/608 ,  G06F2212/651 ,  G11C8/00 ,  G11C11/56 ,  G11C16/08

Abstract: A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far memory addresses mapped to the near memory addresses. The number of entries in the register array is less than the number of pages in near memory. Remapping logic determines that a far memory address of the requested data is absent from the register array and selects an available near memory address from the register array. Remapping logic also initiates writing of the requested data at the far memory address to the selected near memory address. Remapping logic further writes the far memory address to an entry of the register array corresponding to the selected near memory address.

公开(公告)号：US10108549B2

公开(公告)日：2018-10-23

申请号：US14863255

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Christopher B. Wilkerson ,  Zeshan A. Chishti ,  Seth H. Pugsley ,  Alaa R. Alameldeen ,  Shih-Lien L. Lu

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/0862 ,  G06F12/0811 ,  G06F12/084

Abstract: A method is described that includes creating a first data pattern access record for a region of system memory in response to a cache miss at a host side cache for a first memory access request. The first memory access request specifies an address within the region of system memory. The method includes fetching a previously existing data access pattern record for the region from the system memory in response to the cache miss. The previously existing data access pattern record identifies blocks of data within the region that have been previously accessed. The method includes pre-fetching the blocks from the system memory and storing the blocks in the cache.

公开(公告)号：US20240152448A1

公开(公告)日：2024-05-09

申请号：US18284265

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Lingxiang Xiang ,  Christopher J. Hughes

IPC: G06F12/02 ,  G06F12/0811

CPC classification number: G06F12/023 ,  G06F12/0811

Abstract: An embodiment of an integrated circuit may comprise circuitry communicatively coupled to two or more sub-non-uniform memory access clusters (SNCs) to allocate a specified memory space in the two or more SNCs in accordance with a SNC memory allocation policy indicated from a request to initialize the specified memory space. An embodiment of an apparatus may comprise decode circuitry to decode a single instruction, the single instruction to include a field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to provide an indicated SNC memory allocation policy (e.g., a SNC policy hint). Other embodiments are disclosed and claimed.

公开(公告)号：US11526448B2

公开(公告)日：2022-12-13

申请号：US16586251

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Yi Zou ,  Gordon King

IPC: G06F12/0811 ,  G06F12/0873 ,  G06F12/02 ,  G06F13/16 ,  G06F12/0897

Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

公开(公告)号：US10860244B2

公开(公告)日：2020-12-08

申请号：US15854357

申请日：2017-12-26

Applicant: Intel Corporation

Inventor： Binh Pham ,  Christopher B. Wilkerson ,  Alaa R. Alameldeen ,  Zeshan A. Chishti ,  Zhe Wang

IPC: G06F3/06 ,  G06F12/0862 ,  G06F12/0871 ,  G06F12/1027 ,  G06F12/0897 ,  G06F12/1045 ,  G06F12/128 ,  G06F12/14 ,  G06F12/123

Abstract: An apparatus is described that includes a memory controller to couple to a multi-level memory characterized by a faster higher level and a slower lower level. The memory controller having early demotion logic circuitry to demote a page from the higher level to the lower level without system software having to instruct the memory controller to demote the page and before the system software promotes another page from the lower level to the higher level.

公开(公告)号：US10452312B2

公开(公告)日：2019-10-22

申请号：US15396204

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Zhe Wang ,  Zeshan A. Chishti ,  Muthukumar P. Swaminathan ,  Alaa R. Alameldeen ,  Kunal A. Khochare ,  Jason A. Gayman

IPC: G06F3/06 ,  G11C16/34 ,  G11C16/26

Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively. A second voltage level is used to read data from read addresses that do not map to one of the first and the second level indications the first and second level data structures, respectively.

公开(公告)号：US10417135B2

公开(公告)日：2019-09-17

申请号：US15718071

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Zeshan A. Chishti ,  Alaa R. Alameldeen ,  Rajat Agarwal

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/10 ,  G06F12/0877 ,  G06F12/0862 ,  G06F12/128 ,  G06F12/0888 ,  G06F12/1009 ,  G06F12/0817

Abstract: Systems, apparatuses and methods may provide for technology to maintain a prediction table that tracks missed page addresses with respect to a first memory. If an access request does not correspond to any valid page addresses in the prediction table, the access request may be sent to the first memory. If the access request corresponds to a valid page address in the prediction table, the access request may be sent to the first memory and a second memory in parallel, wherein the first memory is associated with a shorter access time than the second memory.

公开(公告)号：US11544093B2

公开(公告)日：2023-01-03

申请号：US16586859

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Andrew V. Anderson ,  Alaa R. Alameldeen ,  Andrew M. Rudoff

IPC: G06F9/455

Abstract: Examples herein relate to checkpoint replication and copying of updated checkpoint data. For example, a memory controller coupled to a memory can receive a write request with an associated address to write or update checkpoint data and track updates to checkpoint data based on at least two levels of memory region sizes. A first level is associated with a larger memory region size than a memory region size associated with the second level. In some examples, the first level is a cache-line memory region size and the second level is a page memory region size. Updates to the checkpoint data can be tracked at the second level unless an update was previously tracked at the first level. Reduced amounts of updated checkpoint data can be transmitted during a checkpoint replication by using multiple region size trackers.

公开(公告)号：US11074188B2

公开(公告)日：2021-07-27

申请号：US16278509

申请日：2019-02-18

Applicant: Intel Corporation

Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Lidia Warnes ,  Andy M. Rudoff ,  Muthukumar P. Swaminathan

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/02 ,  G06F12/0893

Abstract: A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

公开(公告)号：US10261901B2

公开(公告)日：2019-04-16

申请号：US14865617

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Zhe Wang ,  Christopher B. Wilkerson ,  Zeshan A. Chishti ,  Seth H. Pugsley ,  Alaa R. Alameldeen ,  Shih-Lien L. Lu

IPC: G06F12/00 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/0893 ,  G06F13/00 ,  G06F13/28

Abstract: An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.