公开(公告)号：US20250118630A1

公开(公告)日：2025-04-10

申请号：US18377672

申请日：2023-10-06

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Junli Wang ,  Kisik Choi ,  Koichi Motoyama ,  Nicholas Anthony Lanzillo ,  Biswanath Senapati ,  Albert M. Chu ,  Brent A. Anderson ,  Chen Zhang ,  Tenko Yamashita

IPC: H01L23/48 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor structure includes an upper-level CMOS transistor layer having a plurality of upper-level N-type and P-type field effect transistors; and a frontside interconnect layer above, and interconnected with, the upper-level transistor layer. The frontside interconnect layer includes frontside power rails and frontside signal wiring, and at least three frontside interconnect layer metal levels. A lower-level CMOS transistor layer has a plurality of lower-level N-type and P-type field effect transistors; and a backside interconnect layer below, and interconnected with, the lower-level transistor layer. The backside interconnect layer includes backside power rails and backside signal wiring and at least three backside interconnect layer metal levels. At a peripheral region of the structure, at least one conductive interconnection is provided between a third or higher of the at least three frontside interconnect layer metal levels and a third or lower of the at least three backside interconnect layer metal levels.

公开(公告)号：US20240421037A1

公开(公告)日：2024-12-19

申请号：US18337211

申请日：2023-06-19

Applicant: International Business Machines Corporation

Inventor： Lijuan Zou ,  Shahrukh Khan ,  Biswanath Senapati ,  Ruilong Xie

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A plurality of nanosheet recesses are formed within a substrate. A placeholder structure is formed on a bottom surface within each nanosheet recess. A first source/drain region is formed within a first nanosheet recess. A second source/drain region is formed within the second nanosheet recess. The semiconductor structure is flipped. The substrate is removed respective to a sidewall spacer of the placeholder structure and a first etch stop layer of the placeholder structure. Backside interlayer dielectric is formed. A backside contact trench to the second source drain region is formed by removing a portion of the backside interlayer dielectric over the second source/drain region and removing exposed portions of the first etch stop layer, the sidewall spacer, and a silicon buffer layer of the placeholder structure. A backside contact is formed within the trench.

公开(公告)号：US20240220696A1

公开(公告)日：2024-07-04

申请号：US18092126

申请日：2022-12-30

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Leon Sigal ,  Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Biswanath Senapati ,  Lawrence A. Clevenger

IPC: G06F30/392 ,  G06F30/33 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/33 ,  G06F30/394 ,  G06F2119/18

Abstract: A semiconductor structure includes a first backside metal rail that extends across the structure and a second backside metal rail parallel and adjacent to the first backside metal rail. The first and second backside metal rails bound a first circuit row. The structure also includes a backside signal wire that interrupts the second backside metal rail; and a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail. The second and third backside metal rails bound a second circuit row. The structure also includes gate metal pitches, which extend across the structure perpendicular to the backside metal rails. The structure also includes a frontside signal wire above the gate metal pitches; and a signal via that penetrates the structure and connects the backside signal wire to the frontside signal wire.

公开(公告)号：US20250107197A1

公开(公告)日：2025-03-27

申请号：US18471645

申请日：2023-09-21

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Shahrukh Khan ,  Biswanath Senapati ,  Julien Frougier ,  Min Gyu Sung

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device that includes a stack of nanostructure material layers overlying a substrate, wherein a gate all around structure is present on a channel region portion for the stack of nanostructure material layers. A bottom source and drain region is present on a first side of the channel region portion, wherein the bottoms source and drain region is composed by a first epitaxial semiconductor material that has a confinement sidewall spacer in direct contact with sidewalls of the first epitaxial semiconductor material defining a lateral dimension for the epitaxial semiconductor material. An upper source and drain region is present on a second side of the channel region portion for the stack of nanostructure material layers. The upper source and drain region is composed of a second epitaxial semiconductor material that partially extends over the confinement sidewall spacer.

公开(公告)号：US20250031430A1

公开(公告)日：2025-01-23

申请号：US18356291

申请日：2023-07-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shahrukh Khan ,  Biswanath Senapati ,  Utkarsh Bajpai ,  Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Tenko Yamashita ,  John Christopher Arnold ,  Chen Zhang ,  Terence B. Hook ,  Junli Wang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: A microelectronic structure includes a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices. Each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor. A gate cut located between the first row of stacked nano devices and the second row stacked nano devices. An interconnect located within gate cut. The interconnect is connected to a source/drain of one of the lower stacked transistors and the interconnect includes a non-uniform backside surface.

公开(公告)号：US20240421156A1

公开(公告)日：2024-12-19

申请号：US18334817

申请日：2023-06-14

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Biswanath Senapati ,  Albert M. Chu ,  Brent A. Anderson

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor structure includes a first set of transistors in a first level, the first set of transistors having a first gate pitch and a first cell height, and a second set of transistors in a second level, the second set of transistors having a second gate pitch and a second cell height. The second level is vertically stacked over the first level, the first gate pitch is different than the second gate pitch, and the first cell height is different than the second cell height.

公开(公告)号：US20240371729A1

公开(公告)日：2024-11-07

申请号：US18312613

申请日：2023-05-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Biswanath Senapati ,  David Wolpert ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Leon Sigal ,  Brent A. Anderson ,  Albert M. Chu ,  Reinaldo Vega

IPC: H01L23/48 ,  H01L29/417

Abstract: A semiconductor structure including a gate contact above and in direct contact with a top surface of a gate. a backside wiring layer below a backside power delivery network. and a contact via extending between the gate contact and the backside wiring layer.

公开(公告)号：US20240178050A1

公开(公告)日：2024-05-30

申请号：US18059098

申请日：2022-11-28

Applicant: International Business Machines Corporation

Inventor： Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Ruilong Xie ,  Biswanath Senapati ,  Seiji Munetoh ,  Lawrence A. Clevenger

IPC: H01L21/74 ,  H01L21/822 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L21/743 ,  H01L21/8221 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0922

Abstract: One or more systems, devices, and/or methods of fabrication provided herein relate to adjacent buried power rail for stacked field-effect transistor architecture. According to one embodiment, a semiconductor device can comprise a first transistor stacked on a second transistor, wherein the first transistor is offset laterally from the second transistor, and a first buried power rail and a second buried power rail, wherein the first buried power rail is coupled to the first transistor and the second buried power rail is coupled to the second transistor.