公开(公告)号：US20240413085A1

公开(公告)日：2024-12-12

申请号：US18332947

申请日：2023-06-12

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Biswanath Senapati ,  Nicholas Anthony Lanzillo ,  Shahrukh Khan

IPC: H01L23/528 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source/drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source/drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source/drain contact disposed on a first portion of a sidewall and a top surface of the second source/drain region, a first metal via connected to the frontside source/drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.

公开(公告)号：US20250081525A1

公开(公告)日：2025-03-06

申请号：US18459012

申请日：2023-08-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  James P. Mazza ,  Shahrukh Khan ,  Iqbal Rashid Saraf ,  Biswanath Senapati ,  Tenko Yamashita

IPC: H01L29/417 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a first source/drain region connected to a back end of line (BEOL) through a first contact and a first via, and a second source/drain region connected to the BEOL through a second contact, a lateral contact, and a second via. The first via passes through the lateral contact.

公开(公告)号：US20240215266A1

公开(公告)日：2024-06-27

申请号：US18069769

申请日：2022-12-21

Applicant: International Business Machines Corporation

Inventor： Biswanath Senapati ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Albert M. Chu ,  Ruilong Xie ,  Seiji Munetoh

IPC: H10B63/00

CPC classification number: H10B63/80 ,  H10B63/30

Abstract: A semiconductor structure is provided that includes a resistive random access memory located on a surface of a bitline that is embedded in a shallow trench isolation structure. The structure can further include a source line that is present above the bitline or embedded in the shallow trench isolation structure.

公开(公告)号：US20230187314A1

公开(公告)日：2023-06-15

申请号：US17551457

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Biswanath Senapati ,  Seiji Munetoh ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Geoffrey Burr ,  Kohji Hosokawa

IPC: H01L23/48 ,  H01L27/24 ,  H01L23/532 ,  H01L21/768 ,  G11C13/00

CPC classification number: H01L23/481 ,  G11C13/0004 ,  G11C13/0038 ,  H01L21/76898 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L27/2463

Abstract: A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.

公开(公告)号：US20250072113A1

公开(公告)日：2025-02-27

申请号：US18453285

申请日：2023-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  James P. Mazza ,  Shahrukh Khan ,  Iqbal Rashid Saraf ,  Biswanath Senapati ,  Tenko Yamashita

IPC: H01L27/12

Abstract: A semiconductor device includes a first source/drain region, a first contact over the first source/drain region, a second source/drain region, and a lateral contact connecting the second source/drain region to a back end of line (BEOL). Portions of the first contact are recessed, and the lateral contact overlaps with the recessed portions of the first contact. The first source/drain region is formed over the second source/drain region.

公开(公告)号：US20250006736A1

公开(公告)日：2025-01-02

申请号：US18214682

申请日：2023-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Biswanath Senapati ,  Shahrukh Khan ,  Utkarsh Bajpai ,  Terence Hook ,  Chen Zhang ,  Junli Wang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

公开(公告)号：US12148682B2

公开(公告)日：2024-11-19

申请号：US17551457

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Biswanath Senapati ,  Seiji Munetoh ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Geoffrey Burr ,  Kohji Hosokawa

IPC: G11C13/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H10B63/00

Abstract: A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.

公开(公告)号：US20240162118A1

公开(公告)日：2024-05-16

申请号：US17986276

申请日：2022-11-14

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Biswanath Senapati ,  David Wolpert ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Leon Sigal

IPC: H01L23/48 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/481 ,  H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor structure is provided that includes a gate structure that is wired to a backside signal line through a backside gate contact extension and a backside skip-level through via. The backside skip-level through via has a dielectric spacer located on a sidewall thereof and a portion of the backside skip-level through via is positioned between a pair of backside power rails that are located in a first backside metal level that is located beneath a second backside metal level that includes the backside signal line.

公开(公告)号：US20240079326A1

公开(公告)日：2024-03-07

申请号：US17903342

申请日：2022-09-06

Applicant: International Business Machines Corporation

Inventor： Biswanath Senapati ,  SEIJI MUNETOH ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Geoffrey Burr ,  Kohji Hosokawa

IPC: H01L23/528 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L23/5286 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/16

Abstract: An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.

公开(公告)号：US20250125261A1

公开(公告)日：2025-04-17

申请号：US18488236

申请日：2023-10-17

Applicant: International Business Machines Corporation

Inventor： Biswanath Senapati ,  Shahrukh Khan ,  Utkarsh Bajpai ,  Ruilong Xie ,  Indira Seshadri ,  Tenko Yamashita

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes forming a first stage of a multi-stage via in a semiconductor structure utilizing processing from a first side of the semiconductor structure, the first stage of the multi-stage via having a first surface and a second surface opposite the first surface. The method also includes forming a second stage of the multi-stage via utilizing processing from a second side of the semiconductor structure, the first stage of the multi-stage via having a first surface and a second surface opposite the first surface. The first surface of the first stage of the multi-stage via is proximate the first side of the semiconductor structure, the first surface of the second stage of the multi-stage via is proximate the second side of the semiconductor structure, and the second surface of the first stage of the multi-stage via abuts the second surface of the second stage of the multi-stage via.