公开(公告)号：US20190236024A1

公开(公告)日：2019-08-01

申请号：US16377509

申请日：2019-04-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe BRANDT ,  Markus HELMS ,  Christian JACOBI ,  Markus KALTENBACH ,  Thomas KOEHLER ,  Frank LEHNERT

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F9/45558 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

公开(公告)号：US20180276138A1

公开(公告)日：2018-09-27

申请号：US15465763

申请日：2017-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe BRANDT ,  Markus HELMS ,  Christian JACOBI ,  Markus KALTENBACH ,  Thomas KOEHLER ,  Frank LEHNERT

IPC: G06F12/1009 ,  G06F12/0875

Abstract: A translation engine for a processor system to translate virtual memory addresses to physical addresses of a main memory of a computer system is provided, where a sequence of accesses to multiple address translation tables is performed to support a computer system virtualization level. The translation engine includes: a first pipeline having at least, a first pipeline stage to receive a value for an original address or an address translation table entry requested in a previous pass through the first pipeline; a second pipeline stage using the value as an operand in a translation operation eventually yielding the address translation result or yielding a table index to an entry in a next address translation table; and a third pipeline stage issuing a read request for the entry in the next address translation table.

公开(公告)号：US20180260336A1

公开(公告)日：2018-09-13

申请号：US15454243

申请日：2017-03-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe BRANDT ,  Markus HELMS ,  Christian JACOBI ,  Markus KALTENBACH ,  Thomas KOEHLER ,  Frank LEHNERT

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F9/45558 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

公开(公告)号：US20170163283A1

公开(公告)日：2017-06-08

申请号：US15223328

申请日：2016-07-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. BRADBURY ,  Markus HELMS ,  Christian JACOBI ,  Aditya N. PURANIK ,  Christian ZOELLIN

IPC: H03M7/30 ,  H03M7/40 ,  G06F17/30 ,  G06F3/06 ,  G06F17/27

CPC classification number: G06F17/2705 ,  G06F3/0608 ,  G06F3/0626 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F16/2365 ,  G06F16/9027 ,  H03M7/3079 ,  H03M7/3088 ,  H03M7/40

Abstract: A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.

公开(公告)号：US20160147533A1

公开(公告)日：2016-05-26

申请号：US14995337

申请日：2016-01-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. BRADBURY ,  Michael K. GSCHWIND ,  Christian JACOBI ,  Eric M. SCHWARZ ,  Timothy J. SLEGEL

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/3824 ,  G06F9/3861 ,  G06F9/45516

Abstract: A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.

公开(公告)号：US20230318286A1

公开(公告)日：2023-10-05

申请号：US17657989

申请日：2022-04-05

Applicant: International Business Machines Corporation

Inventor： Adam Benjamin COLLURA ,  Michael ROMAIN ,  William V. HUOTT ,  Pawel OWCZARCZYK ,  Christian JACOBI ,  Anthony SAPORITO ,  Chung-Lung K. SHUM ,  Alper BUYUKTOSUNOGLU ,  Tobias WEBEL ,  Michael Joseph CADIGAN, JR. ,  Paul Jacob LOGSDON ,  Sean Michael CAREY ,  Stefan PAYER ,  Karl Evan Smock ANDERSON ,  Mark CICHANOWSKI

IPC: H02H9/04 ,  G06F1/28

CPC classification number: H02H9/04 ,  G06F1/28

Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

公开(公告)号：US20200159663A1

公开(公告)日：2020-05-21

申请号：US16752783

申请日：2020-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jonathan D. BRADBURY ,  Michael K. GSCHWIND ,  Christian JACOBI ,  Chung-Lung K. SHUM

IPC: G06F12/0862 ,  G06F12/084 ,  G06F13/16 ,  G06F12/0811

Abstract: Controlling a rate of prefetching based on bus bandwidth. A determination is made as to whether a rate of prefetching data from memory into a cache is to be changed. This determination is based on bus utilization, and includes identifying a most utilized bus of a plurality of buses used for the prefetch of data, and monitoring utilization of the most utilized bus. The determination whether the rate of prefetching is to be changed is based on the monitoring. Based on determining that the rate is to be changed, the rate of prefetching is changed.

公开(公告)号：US20190236025A1

公开(公告)日：2019-08-01

申请号：US16377556

申请日：2019-04-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Uwe BRANDT ,  Markus HELMS ,  Christian JACOBI ,  Markus KALTENBACH ,  Thomas KOEHLER ,  Frank LEHNERT

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F9/45558 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/1056 ,  G06F2212/151 ,  G06F2212/651 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels. In operation, based on the first translation engine performing a guest level translation, the second translation engine may perform a host level translation of a resulting guest non-virtual address to a host non-virtual address based on the guest level translation by the first translation engine.

公开(公告)号：US20190042469A1

公开(公告)日：2019-02-07

申请号：US15815378

申请日：2017-11-16

Applicant: International Business Machines Corporation

Inventor： Dwifuzi COE ,  Christian JACOBI ,  Markus KALTENBACH ,  Eyal NAOR ,  Martin RECKTENWALD

IPC: G06F12/1045 ,  G06F12/0862 ,  G06F12/0811

Abstract: A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.

公开(公告)号：US20190042468A1

公开(公告)日：2019-02-07

申请号：US15669108

申请日：2017-08-04

Applicant: International Business Machines Corporation

Inventor： Dwifuzi COE ,  Christian JACOBI ,  Markus KALTENBACH ,  Eyal NAOR ,  Martin RECKTENWALD

IPC: G06F12/1045 ,  G06F12/0811 ,  G06F12/0862

Abstract: A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.