公开(公告)号：US20250159963A1

公开(公告)日：2025-05-15

申请号：US18508541

申请日：2023-11-14

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  Nicholas Anthony Lanzillo ,  David Wolpert ,  James P. Mazza

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A field effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end of the active region and a drain at a second end of the active region. The gate extends across the active region and includes at least one end extending past a corresponding edge of the active region by a sub-lithographic dimension.

公开(公告)号：US20240371728A1

公开(公告)日：2024-11-07

申请号：US18141552

申请日：2023-05-01

Applicant: International Business Machines Corporation

Inventor： Albert M. Chu ,  Junli Wang ,  Brent A. Anderson ,  Leon Sigal ,  David Wolpert ,  Ruilong Xie ,  Jay William Strane

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor structure comprises a first transistor and a second transistor. The first transistor comprises a first input source/drain region and a first output source/drain region, and the second transistor comprises a second input source/drain region and a second output source/drain region. The first input source/drain region and the second input source/drain region are connected to a first source/drain contact, and the first output source/drain region and the second output source/drain region are connected to a second source/drain contact. The first source/drain contact and the second source/drain contact on a same side of the semiconductor structure.

公开(公告)号：US20240297167A1

公开(公告)日：2024-09-05

申请号：US18176551

申请日：2023-03-01

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Brent A. Anderson ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Reinaldo Vega ,  David Wolpert

IPC: H01L27/02 ,  H01L21/768 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L21/76877 ,  H01L27/11807 ,  H01L2027/11831

Abstract: A semiconductor structure includes a first plurality of backside power rail interconnects located within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. A first isolation region is located between the first cell height region of the substrate and the second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. The second isolation region electrically separates the adjacent power rail interconnects.

公开(公告)号：US12057387B2

公开(公告)日：2024-08-06

申请号：US17110381

申请日：2020-12-03

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  David Wolpert ,  Takashi Ando ,  Praneet Adusumilli ,  Cheng Chi

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/5286 ,  H01L28/55 ,  H01L29/4236 ,  H01L29/66181 ,  H01L29/945

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.

公开(公告)号：US20240234306A9

公开(公告)日：2024-07-11

申请号：US17969773

申请日：2022-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Nicholas Anthony Lanzillo ,  Takashi Ando ,  David Wolpert ,  Albert M. Chu ,  Albert M. Young

IPC: H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/32139 ,  H01L21/76892 ,  H01L23/5226

Abstract: A semiconductor structure is presented including a first level of interconnect wiring separated into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment and a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring. A distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.

公开(公告)号：US11754615B2

公开(公告)日：2023-09-12

申请号：US17480551

申请日：2021-09-21

Applicant: International Business Machines Corporation

Inventor： Christopher Gonzalez ,  David Wolpert ,  Michael Hemsley Wood

IPC: G01R31/26 ,  G01R31/28 ,  G06F30/3312 ,  G06F117/12 ,  G06F119/12

CPC classification number: G01R31/2623 ,  G01R31/2884 ,  G06F30/3312 ,  G06F2117/12 ,  G06F2119/12

Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

公开(公告)号：US20230251299A1

公开(公告)日：2023-08-10

申请号：US18296519

申请日：2023-04-06

Applicant: International Business Machines Corporation

Inventor： Christopher Gonzalez ,  David Wolpert ,  Michael Hemsley Wood

IPC: G01R31/26 ,  G01R31/28 ,  G06F30/3312

CPC classification number: G01R31/2623 ,  G01R31/2884 ,  G06F30/3312 ,  G06F2117/12

Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

公开(公告)号：US11308257B1

公开(公告)日：2022-04-19

申请号：US17122550

申请日：2020-12-15

Applicant: International Business Machines Corporation

Inventor： Dureseti Chidambarrao ,  David Wolpert ,  Atsushi Ogino ,  Matthew T. Guzowski ,  Steven Paul Ostrander ,  Tuhin Sinha ,  Michael Stewart Gray

IPC: G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  H01L23/48 ,  G06F119/14

Abstract: A structure including a plurality of dielectric regions is described. The structure can include a rivet cell. The rivet cell can include a set of stacked vias. The rivet cell can extend through a stress hotspot of the structure. A length of the rivet cell can thread through at least one dielectric region among the plurality of dielectric regions. The rivet cell can be among a number of rivet cells inserted in the stress hotspot. The stress hotspot can be among a plurality of stress hotspots across the structure. A length of the rivet cell can be based on a model of a relationship between the length of the rivet cell and an energy release rate of the structure. The rivet cell can thread through an interface between a first dielectric region and a second dielectric region having different dielectric constants.

公开(公告)号：US10831980B2

公开(公告)日：2020-11-10

申请号：US16553463

申请日：2019-08-28

Applicant: International Business Machines Corporation

Inventor： Alan P. Wagstaff ,  David Wolpert

IPC: G06F30/398 ,  G06F30/394 ,  G06F111/20

Abstract: Using unused wires on VLSI chips for power supply decoupling including generating a VLSI chip design by: identifying floating wires in a VLSI chip; placing a via at each intersection between each floating wire and a power rail; determining a number of design rule violations for each via at each intersection; resolving the design rule violations for each via not on a major power rail; resolving the design rule violations for each via on a major power rail after resolving the design rule violations for each via not on a major power rail; after resolving the design rule violations for each via on a major power rail, identifying floating wires without a via; and for each floating wire without a via, identify an intersection with a least number of design rule violations and resolve the number of design rule violations by removing adjacent vias on adjacent wires.

公开(公告)号：US20190179994A1

公开(公告)日：2019-06-13

申请号：US15838520

申请日：2017-12-12

Applicant: International Business Machines Corporation

Inventor： Laura R. Darden ,  David Wolpert

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081 ,  G06F2217/12

Abstract: Embodiments of the invention are directed to methods, systems, and computer program products for the hierarchical management of self-aligned double patterning (SADP) trim shapes. Non-limiting embodiments of the invention include receiving, by a processor, one or more virtual trim shapes at a boundary between a parent hierarchy block and a child hierarchy block. The trim shapes are aligned to a legal trim grid. The processor then places one or more trim shapes aligned with the legal trim grid.