公开(公告)号：US20180069027A1

公开(公告)日：2018-03-08

申请号：US15796429

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Derrick Liu ,  Chun Wing Yeung

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L21/308 ,  H01L29/161

Abstract: A semiconductor structure includes a stained fin, a gate upon the strain fin, and a spacer upon a sidewall of the gate and upon an end surface of the strained fin. The end surface of the strained fin is coplanar with a sidewall of the gate. The spacer limits relaxation of the strained fin.

公开(公告)号：US20160351590A1

公开(公告)日：2016-12-01

申请号：US14722237

申请日：2015-05-27

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Derrick Liu ,  Chun Wing Yeung

IPC: H01L27/12 ,  H01L21/308 ,  H01L21/84 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

Abstract translation: 半导体结构包括第一应变翅片部分和第二应变翅片部分，在相应的应变翅片部分上的一对无效内部门结构，以及在非活性内部门结构的外侧壁表面上的间隔物， 内门结构，以及在第一应变翅片部分和第二应变翅片部分端表面上。 第一应变翅片部分和第二应变翅片部分端面与非活性内部门结构的相应的内侧壁表面共面。 形成在端面上的间隔限制了第一应变翅片部分和第二应变翅片部分的松弛，并且限制了第一应变翅片部分和第二应变翅片部分之间的短路。

公开(公告)号：US08871549B2

公开(公告)日：2014-10-28

申请号：US13767024

申请日：2013-02-14

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Derrick Liu

IPC: H01L21/00 ,  H01L29/66 ,  G01N27/414

CPC classification number: G01N27/414 ,  G01N27/4145 ,  G01N27/4148 ,  H01L29/66477

Abstract: Device structures, fabrication methods, and design structures for a biological and chemical sensor used to detect a property of a substance. The device structure includes a drain and a source of a field effect transistor formed at a frontside of a substrate. A sensing layer is formed at a backside of the substrate. The sensing layer is configured to receive the substance.

Abstract translation: 用于检测物质性质的生物和化学传感器的装置结构，制造方法和设计结构。 器件结构包括形成在衬底前侧的场效应晶体管的漏极和源极。 感光层形成在基板的背面。 感测层被配置为接收物质。

公开(公告)号：US11195969B2

公开(公告)日：2021-12-07

申请号：US16053939

申请日：2018-08-03

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Derrick Liu ,  Daniel S. Vanslette

IPC: H01L31/18 ,  H01L31/0224 ,  H01L33/00 ,  H01L33/42 ,  H01L51/00 ,  B82Y10/00 ,  H01B1/24 ,  H05K3/10 ,  B82Y30/00

Abstract: A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in a disorderly arrangement on a substrate. The metal silicide nanowire network can be formed by applying a solution that contains silicon nanowires onto the substrate, forming a metal layer on the silicon nanowires, and performing a silicidation anneal such that the metal silicide nanowires are fused together in a disorderly arrangement, forming a mesh. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.

公开(公告)号：US10170593B2

公开(公告)日：2019-01-01

申请号：US15848433

申请日：2017-12-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L27/11 ,  H01L27/11529

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.

公开(公告)号：US20180358504A1

公开(公告)日：2018-12-13

申请号：US16053959

申请日：2018-08-03

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Derrick Liu ,  Daniel S. Vanslette

IPC: H01L31/18 ,  H01L33/42 ,  H01L31/0224 ,  H01L33/00 ,  B82Y10/00 ,  H01L51/00 ,  B82Y30/00 ,  H01B1/24 ,  H05K3/10

CPC classification number: H01L31/1884 ,  B82Y10/00 ,  B82Y30/00 ,  H01B1/24 ,  H01L31/022408 ,  H01L31/022425 ,  H01L31/022466 ,  H01L33/005 ,  H01L33/42 ,  H01L51/0021 ,  H05K3/105 ,  H05K2201/0108 ,  H05K2201/026 ,  H05K2203/1194 ,  Y02E10/50

Abstract: A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in an orderly arrangement on a substrate. The metal silicide nanowire network can be formed by printing a first set of multiple parallel silicon nanowires on the substrate and printing a second set of multiple parallel silicon nanowires over the first set of multiple parallel silicon nanowires such that said first set is perpendicular to said second set. A metal layer can be formed on the silicon nanowires. A silicidation anneal process is performed such that metal silicide nanowires are formed and fused together in an orderly arrangement, forming a grid network. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.

公开(公告)号：US20180342642A1

公开(公告)日：2018-11-29

申请号：US16053939

申请日：2018-08-03

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Derrick Liu ,  Daniel S. Vanslette

IPC: H01L31/18 ,  H01L33/42 ,  H01L31/0224 ,  H01L33/00 ,  B82Y10/00 ,  H01L51/00 ,  B82Y30/00 ,  H01B1/24 ,  H05K3/10

Abstract: A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in a disorderly arrangement on a substrate. The metal silicide nanowire network can be formed by applying a solution that contains silicon nanowires onto the substrate, forming a metal layer on the silicon nanowires, and performing a silicidation anneal such that the metal silicide nanowires are fused together in a disorderly arrangement, forming a mesh. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.

公开(公告)号：US10121853B2

公开(公告)日：2018-11-06

申请号：US15794636

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US20180122813A1

公开(公告)日：2018-05-03

申请号：US15848433

申请日：2017-12-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/8258 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/11529 ,  H01L29/42376 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/7855

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.

公开(公告)号：US09922983B1

公开(公告)日：2018-03-20

申请号：US15273224

申请日：2016-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/088 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8258 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/11529 ,  H01L29/42376 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/7855

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.