公开(公告)号：US11107814B2

公开(公告)日：2021-08-31

申请号：US16847451

申请日：2020-04-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Junli Wang ,  Michael P. Belyansky

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

公开(公告)号：US20210119016A1

公开(公告)日：2021-04-22

申请号：US17136735

申请日：2020-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael P. Belyansky ,  Oleg Gluschenkov

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

Abstract: In accordance with an embodiment of the present invention, a method and semiconductor device is described, including forming a plurality of gaps of variable size between device features, each of the gaps including vertical sidewalls perpendicular to a substrate surface and a horizontal surface parallel to the substrate surface. Spacer material is directionally deposited concurrently on the horizontal surface in each gap and in a flat area using a total flow rate of gaseous precursors that minimizes gap-loading in a smallest gap compared to the flat area such that the spacer material is deposited on the substrate surface in each gap and in the flat area to a uniform thickness.

公开(公告)号：US10741663B1

公开(公告)日：2020-08-11

申请号：US16374732

申请日：2019-04-03

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Michael P. Belyansky

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L27/092 ,  H01L21/28 ,  H01L21/8238

Abstract: A vertical transport field-effect transistor includes gate metal protected by a conformal encapsulation layer. Techniques for fabricating the transistor include depositing the conformal encapsulation layer over the gate metal prior to depositing an additional encapsulation layer such as a nitride layer. The conformal encapsulation layer protects the gate metal during deposition of the additional encapsulation layer, thereby avoiding oxidation or nitridation of the gate metal. The conformal encapsulation layer may be an amorphous silicon layer deposited at relatively low temperature.

公开(公告)号：US10679993B2

公开(公告)日：2020-06-09

申请号：US16182023

申请日：2018-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Junli Wang ,  Michael P. Belyansky

IPC: H01L21/324 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

公开(公告)号：US20200144265A1

公开(公告)日：2020-05-07

申请号：US16182023

申请日：2018-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Junli Wang ,  Michael P. Belyansky

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/02

Abstract: A method of forming a fin field effect transistor complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a plurality of multilayer fin templates and vertical fins on a substrate, wherein one multilayer fin template is on each of the plurality of vertical fins. The method further includes forming a dummy gate layer on the substrate, the plurality of vertical fins, and the multilayer fin templates, and removing a portion of the dummy gate layer from the substrate from between adjacent pairs of the vertical fins. The method further includes forming a fill layer between adjacent pairs of the vertical fins. The method further includes removing a portion of the dummy gate layer from between the fill layer and the vertical fins, and forming a sidewall spacer layer on the fill layer and between the fill layer and the vertical fins.

公开(公告)号：US20200126867A1

公开(公告)日：2020-04-23

申请号：US16163275

申请日：2018-10-17

Applicant: International Business Machines Corporation

Inventor： Huimei Zhou ,  Kangguo Cheng ,  Michael P. Belyansky ,  Oleg Gluschenkov ,  Richard A. Conti ,  James Kelly ,  Balasubramanian Pranatharthiharan

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12 ,  H01L21/765 ,  H01L23/60

Abstract: Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.

公开(公告)号：US20200052125A1

公开(公告)日：2020-02-13

申请号：US16059693

申请日：2018-08-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Ruqiang Bao ,  Michael P. Belyansky ,  Andrew M. Greene ,  Gen Tsutsui

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/02

Abstract: A method of controlling threshold voltage shift that includes forming a first set of channel semiconductor regions on a first portion of a substrate, and forming a second set of channel semiconductor regions on a second portion of the substrate. A gate structure is formed on the first set of channel semiconductor regions and the second set of channel, wherein the gate structure extends from a first portion of the substrate over an isolation region to a second portion of the substrate. A gate cut region is formed in the gate structure over the isolation region. An oxygen scavenging metal containing layer is formed on sidewalls of the gate cut region.

公开(公告)号：US20190207013A1

公开(公告)日：2019-07-04

申请号：US16292146

申请日：2019-03-04

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Andrew Greene ,  Fee Li Lie ,  Huimei Zhou

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.

公开(公告)号：US20190067078A1

公开(公告)日：2019-02-28

申请号：US15688154

申请日：2017-08-28

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Richard A. Conti ,  Dechao Guo ,  Devendra K. Sadana ,  Jay W. Strane

IPC: H01L21/762 ,  H01L21/02

Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.

公开(公告)号：US20180166277A1

公开(公告)日：2018-06-14

申请号：US15825250

申请日：2017-11-29

Applicant: International Business Machines Corporation

Inventor： Michael P. Belyansky ,  Ravi K. Bonam ,  Anuja Desilva ,  Scott Halle

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0337 ,  G03F7/00 ,  H01L21/02172 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/02356 ,  H01L21/0332 ,  H05K999/99

Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.