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公开(公告)号：US20240203881A1
公开(公告)日：2024-06-20
申请号：US18083385
申请日：2022-12-16
发明人： Chen Zhang , Oleg Gluschenkov , Junli Wang , Somnath Ghosh , Dechao Guo
IPC分类号： H01L23/528 , H01L21/8238 , H01L27/092 , H01L29/417
CPC分类号： H01L23/5286 , H01L21/823871 , H01L27/092 , H01L29/41725
摘要： A semiconductor device includes a transistor structure comprising a plurality of source/drain regions. Base portions of the plurality of source/drain regions correspond to a second side of the semiconductor device opposite to a first side of the semiconductor device. A plurality of metal lines are disposed on the second side of the semiconductor device, wherein the plurality of metal lines comprise at least a first metal line and a second metal line. At least one dielectric layer is disposed between the first metal line and the second metal line.
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公开(公告)号：US20230411397A1
公开(公告)日：2023-12-21
申请号：US17807158
申请日：2022-06-16
IPC分类号： H01L27/12 , H01L23/522 , H01L21/84
CPC分类号： H01L27/1203 , H01L23/5226 , H01L21/84
摘要： A microelectronic structure including a stacked transistor having a lower transistor and an upper transistor. A shared contact in contact with a lower source/drain of the first lower transistor and an upper source/drain of the upper transistor. The shared contact includes a silicide layer, a metal plug layer, and a conductive metal layer.
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3.发明授权公开(公告)号：US11562906B2
公开(公告)日：2023-01-24
申请号：US16265784
申请日：2019-02-01
发明人： Oleg Gluschenkov , Zuoguang Liu , Shogo Mochizuki , Hiroaki Niimi , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L21/285 , H01L29/08 , H01L29/24 , H01L29/267 , H01L29/78 , H01L29/66 , H01L21/768
摘要： Techniques for forming a metastable phosphorous P-doped silicon Si source drain contacts are provided. In one aspect, a method for forming n-type source and drain contacts includes the steps of: forming a transistor on a substrate; depositing a dielectric over the transistor; forming contact trenches in the dielectric that extend down to source and drain regions of the transistor; forming an epitaxial material in the contact trenches on the source and drain regions; implanting P into the epitaxial material to form an amorphous P-doped layer; and annealing the amorphous P-doped layer under conditions sufficient to form a crystalline P-doped layer having a homogenous phosphorous concentration that is greater than about 1.5×1021 atoms per cubic centimeter (at./cm3). Transistor devices are also provided utilizing the present P-doped Si source and drain contacts.
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公开(公告)号：US11227922B2
公开(公告)日：2022-01-18
申请号：US16905626
申请日：2020-06-18
发明人： Tao Li , Tsung-Sheng Kang , Ruilong Xie , Alexander Reznicek , Oleg Gluschenkov
IPC分类号： H01L21/02 , H01L21/285 , H01L21/306 , H01L21/768 , H01L23/528 , H01L23/532 , H01L23/535 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/786 , H01L21/3065
摘要： Semiconductor device designs having a buried power rail with a sloped epitaxy buried contact are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate, wherein at least one of the source and drains has a sloped surface; a buried power rail embedded in the substrate; and a buried contact that connects the buried power rail to the sloped surface of the at least one source and drain. Sidewall spacers separate the buried power rail from the substrate. A top of the sloped surface of the at least one source and drain is above a top surface of the buried contact. Methods of forming a semiconductor FET device are also provided.
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公开(公告)号：US11139215B2
公开(公告)日：2021-10-05
申请号：US16983587
申请日：2020-08-03
发明人： Tenko Yamashita , Takashi Ando , Oleg Gluschenkov , Chen Zhang , Koji Watanabe
IPC分类号： H01L21/8238 , H01L21/324 , H01L29/49 , H01L21/762 , H01L21/265 , H01L27/092 , H01L29/786 , H01L21/308
摘要： A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.
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公开(公告)号：US11107968B1
公开(公告)日：2021-08-31
申请号：US16825535
申请日：2020-03-20
摘要： According to an embodiment of the present invention, a quantum mechanical device includes a monolithic crystalline structure. The monolithic crystalline structure includes a first region doped to provide a first superconducting region, and a second region doped to provide a second superconducting region, the second superconducting region being separated from the first superconducting region by an undoped crystalline region. The first and second superconducting regions and the undoped crystalline region form a Josephson junction.
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公开(公告)号：US11088280B2
公开(公告)日：2021-08-10
申请号：US15814540
申请日：2017-11-16
发明人： Veeraraghavan S. Basker , Nicolas L. Breil , Oleg Gluschenkov , Shogo Mochizuki , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092 , H01L29/201 , H01L29/205 , H01L29/207 , H01L29/66
摘要： The disclosure provides for a transistor which may include: a gate stack on a substrate, the gate stack including a gate dielectric and a gate electrode over the gate dielectric; a channel within the substrate and under the gate stack; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion and the second coefficient of diffusion is less than the third coefficient of diffusion.
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公开(公告)号：US11022887B2
公开(公告)日：2021-06-01
申请号：US16675276
申请日：2019-11-06
发明人： Yongan Xu , Jing Guo , Ekmini A. De Silva , Oleg Gluschenkov
IPC分类号： G03F7/20 , H01L21/027 , G03F7/075 , G03F7/085 , G03F7/09
摘要： An EUV lithographic structure and methods according to embodiments of the invention includes an EUV photosensitive resist layer disposed directly on an oxide hardmask layer, wherein the oxide hardmask layer is doped with dopant ions to form a doped oxide hardmask layer so as to improve adhesion between the EUV lithographic structure and the oxide hardmask. The EUV lithographic structure is free of a separate adhesion layer.
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9.发明授权公开(公告)号：US11004984B2
公开(公告)日：2021-05-11
申请号：US16578762
申请日：2019-09-23
发明人： Heng Wu , Oleg Gluschenkov , Lan Yu , Ruilong Xie
IPC分类号： H01L29/786 , H01L29/66 , H01L29/78
摘要： Embodiments of the present invention are directed to forming a nanosheet field effect transistor (FET) having a low resistivity region that reduces the nanosheet external resistance. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. An inner layer is formed over nanosheets in the nanosheet stack. The inner layer includes a first material having a first melting point. An outer layer is formed over the inner layer. The outer layer includes a second material having a second melting point that is lower than the first melting point. A heavily doped region is formed on a surface of the outer layer and the nanosheet stack is annealed at a temperature between the first melting point and the second melting point such that the outer layer is selectively liquified, distributing the dopants throughout the outer layer.
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公开(公告)号：US10777468B1
公开(公告)日：2020-09-15
申请号：US16360353
申请日：2019-03-21
发明人： Chen Zhang , Tenko Yamashita , Kangguo Cheng , Oleg Gluschenkov
IPC分类号： H01L21/8234 , H01L29/423 , H01L21/8238 , H01L21/285 , H01L21/311
摘要： A method of forming a semiconductor structure includes forming a stacked vertical transport field-effect transistor (VTFET) structure and a sacrificial layer in contact with a source/drain region of the stacked vertical transport field-effect transistor structure. A masking layer is formed over the sacrificial layer. The masking layer defines a pattern to be patterned into the sacrificial layer. The sacrificial layer is patterned based on the masking layer to form a patterned sacrificial layer and the masking layer is removed. A portion of the stacked VTFET structure is etched down to a surface of the patterned sacrificial layer and the patterned sacrificial layer is removed to form a channel exposing the source/drain region. A contact material is formed in the etched portion of the stacked vertical transport field-effect transistor structure and in the channel. The contact material is formed in contact with the exposed source/drain region.
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