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公开(公告)号：US10755404B2
公开(公告)日：2020-08-25
申请号：US15834602
申请日：2017-12-07
Applicant: International Business Machines Corporation
Inventor： Chung-Ching Lin , Thomas McCarroll Shaw , Peilin Song , Franco Stellari , Thomas Anthony Wassick
IPC: G06T7/00
Abstract: Techniques that facilitate integrated circuit defect detection using pattern images are provided. In one example, a system generates an equalized pattern image of a pattern image associated with a module under test based on an adaptive contrast equalization technique. The system also identifies a first set of features of the equalized pattern image based on a feature point detection technique and aligns the equalized pattern image with a reference pattern image based on the first set of features and a second set of features of the reference pattern image. Furthermore, the system compares a first set of light intensities of the equalized pattern image to a second set of light intensities of the reference pattern image to identify one or more regions of the module under test that satisfy a defined criterion associated with a defect for the module under test.
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公开(公告)号：US10552278B2
公开(公告)日：2020-02-04
申请号：US16035032
申请日：2018-07-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Keith A. Jenkins , Barry P. Linder , Emily A. Ray , Raphael P. Robertazzi , Peilin Song , James H. Stathis , Kevin G. Stawiasz , Franco Stellari , Alan J. Weger , Emmanuel Yashchin
IPC: G06F11/00 , G06F11/22 , G06F11/24 , G06F11/263
Abstract: A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.
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公开(公告)号：US10515181B2
公开(公告)日：2019-12-24
申请号：US15591691
申请日：2017-05-10
Applicant: International Business Machines Corporation
Inventor： Andrea Bahgat Shehata , Peilin Song , Franco Stellari
Abstract: Techniques facilitating integrated circuit identification and reverse engineering are provided. A computer-implemented method can comprise identifying, by a system operatively coupled to a processor, an element within a first elementary cell of one or more elementary cells of an integrated circuit. The method can also comprise matching, by the system, the element with respective elements across the one or more elementary cells including the first elementary cell. The respective elements can be replicas of the element. Further, matching the element with respective elements can be based on a layout analysis of the integrated circuit.
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公开(公告)号：US10147175B2
公开(公告)日：2018-12-04
申请号：US15414569
申请日：2017-01-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Andrea Bahgat Shehata , Peilin Song , Franco Stellari , Alan J. Weger
Abstract: A computer-implemented device and method for identifying hardware Trojans and defects based on light emissions from Integrated Circuits (ICs) is provided. A measured emissions map is received based on light emissions captured from a sacrificial test IC. The sacrificial test IC is a partially manufactured IC fabricated to include a set of frontend layers of an IC architecture but not a set of backend layers of the IC architecture. The sacrificial test IC also includes a sacrificial layer for powering devices in the partially manufactured IC without the set of backend layers. An expected emissions map is derived from the sacrificial test IC and the measured emissions map is compared with the expected emissions map to identify deviations from the IC architecture in the frontend layers.
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公开(公告)号：US20170122999A1
公开(公告)日：2017-05-04
申请号：US15403462
申请日：2017-01-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Jifeng Chen , Dirk Pfeiffer , Thomas M. Shaw , Peilin Song , Franco Stellari
IPC: G01R31/28 , G01R31/311
CPC classification number: G01R31/2855 , G01R31/281 , G01R31/2817 , G01R31/2858 , G01R31/2879 , G01R31/311
Abstract: Methods for reliability testing include applying a stress voltage to a device under test (DUT); measuring a leakage current across the DUT; triggering measurement of optical emissions from the DUT based on the timing of the measurement of the leakage current; and correlating measurements of the leakage current with measurements of the optical emissions to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.
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Patent Agency Ranking
16.发明申请公开(公告)号：US20160003902A1
公开(公告)日：2016-01-07
申请号：US14722377
申请日：2015-05-27
Applicant: International Business Machines Corporation
Inventor： Dzmitry S. Maliuk , Franco Stellari , Alan J. Weger , Peilin Song
IPC: G01R31/3177
CPC classification number: G01R31/3177 , G01R31/31723 , G01R31/31727 , G01R31/318516 , G01R31/318519 , G01R31/318541 , G01R31/318572
Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.
Abstract translation: 公开了扫描链锁存电路，操作扫描链中的锁存电路的方法，以及其上存储有限定用于在半导体管芯上实例化的扫描链锁存电路的数据结构的计算机可读介质。 在一个实施例中，扫描链锁存电路包括用于保存一个数据值的第一锁存器，用于保存另一个数据值的第二锁存器和多路复用器。 一个数据值被应用于多路复用器的第一数据输入端，并且另一个数据值被应用于多路复用器的第二数据输入端。 交替时钟信号被施加到多路复用器的选择输入端以控制多路复用器的输出，其中多路复用器的输出在保持在两个锁存器中的两个数据值之间以定义的频率切换。
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公开(公告)号：US09088278B2
公开(公告)日：2015-07-21
申请号：US13886805
申请日：2013-05-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Dirk Pfeiffer , Jean-Olivier Plouchart , Peilin Song
IPC: H04L9/20 , H03K19/003
CPC classification number: H03K19/003
Abstract: Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of PUFs are employed to minimize sensitivity to temperature variations as well as other factors that affect the reliability of PUF states. In particular, a PUF system can include PUF elements arranged in series and in parallel with respect to each other to facilitate the measurement of the differentials and generation of a resulting bit sequence for purposes of authenticating the chip. Other embodiments are directed to determining and filtering reliable and unreliable states that can be employed to authenticate a chip.
Abstract translation: 公开了使用物理不可克隆功能（PUF）的芯片认证相关的方法，系统和设备。 在优选的系统中，使用PUF的差异来最小化对温度变化的敏感性以及影响PUF状态的可靠性的其它因素。 特别地，PUF系统可以包括相对于彼此串联并联布置的PUF元件，以促进对差分的测量并产生所得到的位序列以便认证芯片。 其他实施例涉及确定和过滤可用于认证芯片的可靠和不可靠的状态。
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公开(公告)号：US20140327468A1
公开(公告)日：2014-11-06
申请号：US13886805
申请日：2013-05-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Dirk Pfeiffer , Jean-Olivier Plouchart , Peilin Song
IPC: H03K19/003
CPC classification number: H03K19/003
Abstract: Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of PUFs are employed to minimize sensitivity to temperature variations as well as other factors that affect the reliability of PUF states. In particular, a PUF system can include PUF elements arranged in series and in parallel with respect to each other to facilitate the measurement of the differentials and generation of a resulting bit sequence for purposes of authenticating the chip. Other embodiments are directed to determining and filtering reliable and unreliable states that can be employed to authenticate a chip.
Abstract translation: 公开了使用物理不可克隆功能（PUF）的芯片认证相关的方法，系统和设备。 在优选的系统中，使用PUF的差异来最小化对温度变化的敏感性以及影响PUF状态的可靠性的其它因素。 特别地，PUF系统可以包括相对于彼此串联并联布置的PUF元件，以促进对差分的测量并产生所得到的位序列以便认证芯片。 其他实施例涉及确定和过滤可用于认证芯片的可靠和不可靠的状态。
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公开(公告)号：US20220020706A1
公开(公告)日：2022-01-20
申请号：US16933549
申请日：2020-07-20
Applicant: International Business Machines Corporation
Inventor： Jean-Olivier Plouchart , Dirk Pfeiffer , Arvind Kumar , Takashi Ando , Peilin Song
Abstract: A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.
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公开(公告)号：US10755397B2
公开(公告)日：2020-08-25
申请号：US15955974
申请日：2018-04-18
Applicant: International Business Machines Corporation
Inventor： Franco Stellari , Chung-Ching Lin , Peilin Song
Abstract: Systems, computer-implemented methods, and computer program products to focus a microscope. A system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise an analyzer component that can analyze sub-images of respective sample images to identify one or more sub-images having a maximized variance of a gradient derivative corresponding to the one or more sub-images. The respective sample images can be acquired at one or more focal positions along an optical axis of a microscope. The computer executable components can further comprise a selection component that can select an image, from the respective sample images, that comprises the one or more sub-images identified. The computer executable components can also comprise a focus component that, based on a focal position corresponding to the image selected, can focus the microscope to the focal position.
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