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公开(公告)号：US09026981B2
公开(公告)日：2015-05-05
申请号：US14308835
申请日：2014-06-19
Applicant: International Business Machines Corporation
Inventor： Baozhen Li , James H. Stathis , Ernest Y. Wu
CPC classification number: G06F17/5081 , G01R31/2831 , H01L22/14 , H01L22/34
Abstract: Embodiments relate to methods, computer systems and computer program products for performing a dielectric reliability assessment for an advanced semiconductor. Embodiments include receiving data associated with a test of a macro of the advanced semiconductor to a point of dielectric breakdown. Embodiments also include scaling the data for the macro down to a reference area and extracting a parameter for a Weibull distribution from the scaled down data for the reference area. Embodiments further include deriving a cluster factor (α) from the scaled down data for the reference area and projecting a failure rate for a larger area of the advanced semiconductor based on the extracted parameter, the cluster factor and the recorded data associated with the dielectric breakdown of the macro.
Abstract translation: 实施例涉及用于对先进半导体执行电介质可靠性评估的方法，计算机系统和计算机程序产品。 实施例包括将与先进半导体的宏观测试有关的数据接收到介质击穿点。 实施例还包括将宏的数据缩放到参考区域，并从参考区域的缩小数据中提取威布尔分布的参数。 实施例还包括从参考区域的缩小数据导出聚类因子（α），并且基于所提取的参数，聚集因子和与介电击穿相关联的记录数据，为先进半导体的较大面积的故障率投射 的宏。
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2.发明授权Determining appropriateness of sampling integrated circuit test data in the presence of manufacturing variations 有权在存在制造变化的情况下确定采样集成电路测试数据的适当性公开(公告)号：US09287185B1
公开(公告)日：2016-03-15
申请号：US14753771
申请日：2015-06-29
Applicant: International Business Machines Corporation
Inventor： Griselda Bonilla , Baozhen Li , Barry P. Linder , James H. Stathis , Ernest Y. Wu , Kai Zhao
CPC classification number: H01L22/14 , G01R31/2894 , H01L22/20
Abstract: Methods and systems determine an original statistical variance of an original failure distribution of a component (that is common to all chips tested) that occurs during manufacturing of wafers containing such chips. These methods and systems determine a first statistical variance of a reconstructed failure distribution, relative to sample size; and determine a second statistical variance of a mean time to failure of the component, relative to sample size. The first and second statistical variances are combined into a total reconstruction variance. Methods and systems determine whether the original statistical variance is less than the total reconstruction variance to identify whether the process of creating the reconstructed failure distribution can be used. Therefore, these methods and systems prohibit testing of the additional wafers manufactured using the specific wafer design and manufacturing process when on the original statistical variance is less than the total reconstruction variance.
Abstract translation: 方法和系统确定在制造包含这种芯片的晶片期间发生的组件的原始故障分布的原始统计方差（对于所有测试的芯片是常见的）。 这些方法和系统相对于样本大小确定重建失效分布的第一统计方差; 并且相对于样本大小确定组件的平均故障时间的第二统计方差。 第一和第二统计学差异被组合成总重建方差。 方法和系统确定原始统计方差是否小于总重建方差，以确定是否可以使用创建重建失效分布的过程。 因此，当原始统计方差小于总重建方差时，这些方法和系统禁止使用特定晶片设计和制造过程制造的附加晶片的测试。
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公开(公告)号：US08839180B1
公开(公告)日：2014-09-16
申请号：US13899968
申请日：2013-05-22
Applicant: International Business Machines Corporation
Inventor： Baozhen Li , James H. Stathis , Ernest Y. Wu
CPC classification number: G06F17/5081 , G01R31/2831 , H01L22/14 , H01L22/34
Abstract: Embodiments relate to methods, computer systems and computer program products for performing a dielectric reliability assessment for an advanced semiconductor. Embodiments include receiving data associated with a test of a macro of the advanced semiconductor to a point of dielectric breakdown. Embodiments also include scaling the data for the macro down to a reference area and extracting a parameter for a Weibull distribution from the scaled down data for the reference area. Embodiments further include deriving a cluster factor (α) from the scaled down data for the reference area and projecting a failure rate for a larger area of the advanced semiconductor based on the extracted parameter, the cluster factor and the recorded data associated with the dielectric breakdown of the macro.
Abstract translation: 实施例涉及用于对先进半导体执行电介质可靠性评估的方法，计算机系统和计算机程序产品。 实施例包括将与先进半导体的宏观测试有关的数据接收到介质击穿点。 实施例还包括将宏的数据缩放到参考区域，并从参考区域的缩小数据中提取威布尔分布的参数。 实施例还包括从参考区域的缩小数据导出聚类因子（α），并且基于所提取的参数，聚集因子和与介电击穿相关联的记录数据，为先进半导体的较大面积的故障率投射 的宏。
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公开(公告)号：US10552278B2
公开(公告)日：2020-02-04
申请号：US16035032
申请日：2018-07-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Keith A. Jenkins , Barry P. Linder , Emily A. Ray , Raphael P. Robertazzi , Peilin Song , James H. Stathis , Kevin G. Stawiasz , Franco Stellari , Alan J. Weger , Emmanuel Yashchin
IPC: G06F11/00 , G06F11/22 , G06F11/24 , G06F11/263
Abstract: A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.
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公开(公告)号：US10574240B2
公开(公告)日：2020-02-25
申请号：US15445587
申请日：2017-02-28
Applicant: International Business Machines Corporation
Inventor： Keith A. Jenkins , Peilin Song , James H. Stathis , Franco Stellari
Abstract: An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.
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Patent Agency Ranking
公开(公告)号：US20180328979A1
公开(公告)日：2018-11-15
申请号：US15803969
申请日：2017-11-06
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James H. Stathis
Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.
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公开(公告)号：US10102090B2
公开(公告)日：2018-10-16
申请号：US15156136
申请日：2016-05-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Keith A. Jenkins , Barry P. Linder , Emily A. Ray , Raphael P. Robertazzi , Peilin Song , James H. Stathis , Kevin G. Stawiasz , Franco Stellari , Alan J. Weger , Emmanuel Yashchin
IPC: G06F11/00 , G06F11/22 , G06F11/263
Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.
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公开(公告)号：US10746782B2
公开(公告)日：2020-08-18
申请号：US15803969
申请日：2017-11-06
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James H. Stathis
Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.
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公开(公告)号：US10739397B2
公开(公告)日：2020-08-11
申请号：US15591226
申请日：2017-05-10
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James H. Stathis
Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.
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公开(公告)号：US20180328977A1
公开(公告)日：2018-11-15
申请号：US15591226
申请日：2017-05-10
Applicant: International Business Machines Corporation
Inventor： Benjamin D. Briggs , Lawrence A. Clevenger , Nicholas A. Lanzillo , Michael Rizzolo , Theodorus E. Standaert , James H. Stathis
Abstract: Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.
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