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    BTI degradation test circuit
    1.
    发明授权
    BTI degradation test circuit 有权

    公开(公告)号：US10782336B2

    公开(公告)日：2020-09-22

    申请号：US15080937

    申请日：2016-03-25

    Applicant: International Business Machines Corporation

    Inventor： Keith A. Jenkins ,  Barry P. Linder

    IPC: G01R31/3183 ,  G01R31/26 ,  G01R31/3193

    Abstract: Embodiments are directed to a system for measuring a degradation characteristic of a plurality of electronic components. The system includes a parallel stress generator communicatively coupled to the plurality of electronic components, and a serial electronic measuring component communicatively coupled to the plurality of electronic components. The parallel stress generator is configured to generate a plurality of stress signals, apply the plurality of stress signals in parallel to the plurality of electronic components and remove the plurality of stress signals from the plurality of electronic components. The serial electronic measuring component is configured to, subsequent to the removal of the plurality of stress signals, sequentially measure the degradation characteristic of each one of the plurality of electronic components in order to determine their degradation resulting from the applied stress signals.

    Test circuit to isolate HCI degradation
    3.
    发明授权
    Test circuit to isolate HCI degradation 有权

    公开(公告)号：US09866221B2

    公开(公告)日：2018-01-09

    申请号：US15163379

    申请日：2016-05-24

    Applicant: International Business Machines Corporation

    Inventor： Keith A. Jenkins ,  Barry P. Linder

    IPC: H03L7/00 ,  H03K3/03 ,  H03K5/133 ,  G01R31/26 ,  G01R31/317

    CPC classification number: H03L7/00 ,  G01R31/2621 ,  G01R31/31727 ,  G01R31/31937 ,  H03K3/011 ,  H03K3/0315 ,  H03K5/133

    Abstract: Embodiments are directed to a system for synchronizing switching events. The system includes a controller, a clock generator communicatively coupled to the controller and a delay chain communicatively coupled to the controller. The delay chain is configured to perform a plurality of delay chain switching events in response to an input to the delay chain. The controller is configured to initiate a synchronization phase that includes enabling the clock generator to provide as an input to the delay chain a clock generator output at a synchronization frequency, wherein the clock generator output passing through the delay chain synchronizes the plurality of delay chain switching events to occur at the synchronization frequency resulting in a frequency of an output of the delay chain being synchronized to the synchronization frequency of the clock generator output.

    BTI DEGRADATION TEST CIRCUIT
    7.
    发明申请
    BTI DEGRADATION TEST CIRCUIT 审中-公开

    公开(公告)号：US20170276728A1

    公开(公告)日：2017-09-28

    申请号：US15080937

    申请日：2016-03-25

    Applicant: International Business Machines Corporation

    Inventor： Keith A. Jenkins ,  Barry P. Linder

    IPC: G01R31/3183

    Abstract: Embodiments are directed to a system for measuring a degradation characteristic of a plurality of electronic components. The system includes a parallel stress generator communicatively coupled to the plurality of electronic components, and a serial electronic measuring component communicatively coupled to the plurality of electronic components. The parallel stress generator is configured to generate a plurality of stress signals, apply the plurality of stress signals in parallel to the plurality of electronic components and remove the plurality of stress signals from the plurality of electronic components. The serial electronic measuring component is configured to, subsequent to the removal of the plurality of stress signals, sequentially measure the degradation characteristic of each one of the plurality of electronic components in order to determine their degradation resulting from the applied stress signals.

    ON-CHIP LEAKAGE MEASUREMENT
    8.
    发明申请
    ON-CHIP LEAKAGE MEASUREMENT 有权

    公开(公告)号：US20170254846A1

    公开(公告)日：2017-09-07

    申请号：US15060497

    申请日：2016-03-03

    Applicant: International Business Machines Corporation

    Inventor： Chen-Yong Cher ,  Keith A. Jenkins ,  Barry P. Linder

    IPC: G01R31/02 ,  G01R19/165

    CPC classification number: G01R31/025 ,  G01R19/165 ,  G01R31/2884 ,  G01R31/3008

    Abstract: Method of measuring semiconductor device leakage which includes: providing a semiconductor device powered by a supply voltage and having a circuit block of transistors; providing on the semiconductor device a test circuit providing an input to a counter and a fixed-frequency measurement clock to provide a clock signal to the counter; disconnecting a system clock from the circuit block; receiving by the test circuit the supply voltage as an input; initializing the counter; starting the counter when the supply voltage is at or below a first voltage Vhigh; monitoring a decrease of the supply voltage with time; stopping the counter when the supply voltage is at or below a second voltage Vlow such that Vhigh is greater than Vlow; and reading the counter to provide the semiconductor device leakage metric. Also disclosed is an apparatus and a computer program product.

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