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    Early overlay prediction and overlay-aware mask design
    11.
    发明授权
    Early overlay prediction and overlay-aware mask design 有权

    公开(公告)号：US10152567B2

    公开(公告)日：2018-12-11

    申请号：US15862782

    申请日：2018-01-05

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

    IPC: G06F17/50 ,  G03F7/20

    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.

    EARLY OVERLAY PREDICTION AND OVERLAY-AWARE MASK DESIGN
    12.
    发明申请
    EARLY OVERLAY PREDICTION AND OVERLAY-AWARE MASK DESIGN 审中-公开

    公开(公告)号：US20180129774A1

    公开(公告)日：2018-05-10

    申请号：US15862782

    申请日：2018-01-05

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

    IPC: G06F17/50 ,  G03F7/20

    CPC classification number: G06F17/5081 ,  G03F7/70433 ,  G03F7/705 ,  G03F7/70633

    Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.

    Dividing lithography exposure fields to improve semiconductor fabrication
    14.
    发明授权
    Dividing lithography exposure fields to improve semiconductor fabrication 有权
    划分光刻曝光场以改善半导体制造

    公开(公告)号：US09424388B2

    公开(公告)日：2016-08-23

    申请号：US14573535

    申请日：2014-12-17

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F7/70066 ,  G03F7/705 ,  G03F7/70558 ,  G06F2217/12 ,  Y02P90/265

    Abstract: In an approach to determine one or more exposure areas in a reticle field and associated lithography process parameters for the one or more exposure areas, a computer receives a semiconductor design and sends the semiconductor design to a design analysis program. Additionally, the computer receives data from the design analysis program. Furthermore, the computer determines the one or more exposure areas in the reticle field, and at least one lithography process parameter for each exposure area of the one or more exposure areas in the reticle field based, at least in part, on the data received from the design analysis program, the semiconductor design, and one or more clustering algorithms associated with the design analysis program.

    Abstract translation: 在确定掩模版领域中的一个或多个曝光区域和用于一个或多个曝光区域的相关光刻工艺参数的方法中，计算机接收半导体设计并将半导体设计发送到设计分析程序。 此外，计算机从设计分析程序接收数据。 此外，计算机至少部分地基于从所述标线区域中接收的数据确定标线场中的一个或多个曝光区域以及至少一个光刻处理参数，所述至少一个光刻处理参数用于所述标线区域中的所述一个或多个曝光区域的每个曝光区域 设计分析程序，半导体设计以及与设计分析程序相关联的一个或多个聚类算法。

    Measuring metal line spacing in semiconductor devices
    16.
    发明授权
    Measuring metal line spacing in semiconductor devices 有权
    测量半导体器件中的金属线间距

    公开(公告)号：US09157980B2

    公开(公告)日：2015-10-13

    申请号：US13680139

    申请日：2012-11-19

    Applicant: International Business Machines Corporation

    Inventor： Thomas W. Dyer ,  Stephen E. Greco

    IPC: H01L23/52 ,  G01R35/00 ,  H01L21/66

    CPC classification number: G01R35/00 ,  H01L22/34

    Abstract: A test layout structure including a first series of parallel metal lines in a first level, and a first series of contact structures in a second level, the second level being positioned above the first level, the first series of contact structures being positioned at known increments, where the increments are in a direction perpendicular to a length of the first series of parallel metal lines, and where one or more of the first series of contact structures is in electrical contact with one or more of the first series of parallel metal lines.

    Abstract translation: 包括第一级中的第一系列平行金属线和第二级中的第一接触结构系列的测试布局结构，所述第二级位于所述第一级上方，所述第一级接触结构以已知增量 其中所述增量在垂直于所述第一系列平行金属线的长度的方向上，并且其中所述第一系列接触结构中的一个或多个与所述第一系列平行金属线中的一个或多个电接触。

    Reticle data decomposition for focal plane determination in lithographic processes
    18.
    发明授权
    Reticle data decomposition for focal plane determination in lithographic processes 有权
    光刻数据分解用于光刻工艺中的焦平面测定

    公开(公告)号：US09058457B2

    公开(公告)日：2015-06-16

    申请号：US14083578

    申请日：2013-11-19

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Ian P. Stobert ,  Rasit O. Topaloglu

    IPC: G06F17/50 ,  H01L21/66

    CPC classification number: G06F17/5068 ,  G03F9/7026 ,  H01L22/12 ,  H01L22/20

    Abstract: A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different topographies. Reticle design data is received for exposure on the wafer surface, whereby, from the received reticle design data, reticle design data subsets that are each allocated to a corresponding one of the determined plurality of regions are generated. A best fit focal plane is then generated for each of the determined plurality of regions.

    Abstract translation: 提供了在晶片表面的光刻曝光期间确定焦平面的方法。 该方法可以包括接收对应于晶片表面的表面形貌的数据，并且基于与表面形貌对应的接收数据，确定具有基本上不同的拓扑图的多个区域。 接收掩模版设计数据以在晶片表面上曝光，由此，从接收到的掩模版设计数据生成分配给所确定的多个区域中的相应一个的掩模版设计数据子集。 然后为确定的多个区域中的每一个生成最佳拟合焦平面。

    Generation of design shapes for confining stitch-induced via structures
    19.
    发明授权
    Generation of design shapes for confining stitch-induced via structures 有权
    生成限制针迹引导通孔结构的设计形状

    公开(公告)号：US08806393B1

    公开(公告)日：2014-08-12

    申请号：US13849764

    申请日：2013-03-25

    Applicant: International Business Machines Corporation

    Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A design layout includes a conductive line level, at least one underlying conductive line level, and a via design level for vertically interconnecting structures in the conductive line level and the at least one underlying conductive line level. Stitch shapes are identified in the conductive line level. Test shapes are generated to determine whether vias formed in the area of the stitch shapes can extend to the at least one underlying conductive line level without contacting preexisting design shapes in the at least one underlying conductive line level structure and whether a new design shape can be inserted into the at least one underlying conductive line level with electrical isolation. As many new design shapes are inserted as possible to prevent extension of collateral via structures below the top surface of underlying metal line structures in a physical metal interconnect structure implementing the design layout.

    Abstract translation: 设计布局包括导线级别，至少一个底层导电线电平以及用于在导线电平和至少一个底层导线电平线中垂直互连结构的通孔设计级别。 线迹形状在导线级别识别。 产生测试形状以确定在针迹形状的区域中形成的通孔是否可以延伸到至少一个下面的导电线水平，而不会接触至少一个下面的导电线水平结构中的预先存在的设计形状，以及新的设计形状是否可以 通过电气隔离插入至少一个底层导电线路。 尽可能插入许多新的设计形状，以防止通过实施设计布局的物理金属互连结构中下面的金属线结构的顶表面下方的结构延伸抵押物。

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