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公开(公告)号：US11462295B2
公开(公告)日：2022-10-04
申请号：US16845259
申请日：2020-04-10
发明人： Timothy Meehan , Kirk D. Peterson , John B. DeForge , William V. Huott , Uma Srinivasan , Hyong Uk Kim , Michelle E. Finnefrock , Daniel Rodko
IPC分类号： G11C29/00
摘要： A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.
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公开(公告)号：US20210294640A1
公开(公告)日：2021-09-23
申请号：US16820808
申请日：2020-03-17
发明人： K Paul Muller , William V. Huott , Eberhard Engler , Christopher Raymond Conklin , Stephanie Lehrer , Andrew A. Turner
摘要： Aspects of the present invention disclose a method for avoiding overvoltages of a processor chip. The method includes one or more processors identifying one or more processing units of a computing device. The method further includes determining respective activity levels of one or more processing elements of the one or more processing units of the computing device. The method further includes determining respective voltages of the one or more processing units of the computing device. The method further includes regulating the respective voltages of the one or more processing units of the computing device based at least in part on the respective activity levels of the one or more processing elements.
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公开(公告)号：US10897239B1
公开(公告)日：2021-01-19
申请号：US16563104
申请日：2019-09-06
摘要： A method comprises activating an interval timer to expire in a calibration time interval and, in response to the timer expiring, performing an impedance analysis of an electronic network. The impedance analysis can use time-domain reflectometry. Based on the analysis, the method can calibrate a variable impedance device to have a first impedance and re-activate the timer. The method can perform a second impedance analysis based on calibrating the variable impedance device. The method can include determining a drift rate and modifying the calibration time interval. The variable impedance device can comprise a phase-change material (PCM), and the time interval can correspond to a retention time of the PCM and/or a dynamic drift rate. A system comprising a segment of an electronic network, a timer, a variable impedance device, and an impedance tuning system can embody operations of the method.
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公开(公告)号：US10373678B2
公开(公告)日：2019-08-06
申请号：US15826990
申请日：2017-11-30
发明人： William V. Huott , Chandrasekharan Kothandaraman , Adam J. McPadden , Uma Srinivasan , Stephen Wu
IPC分类号： G11C11/419 , G11C29/50 , G11C29/12 , G11C7/04 , G11C29/02 , G11C29/06 , G11C11/417
摘要： Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.
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公开(公告)号：US20180074109A1
公开(公告)日：2018-03-15
申请号：US15817402
申请日：2017-11-20
CPC分类号： G01R31/025 , G01R31/024 , G01R31/2851 , G01R31/2856 , G01R31/2858 , G01R31/3008
摘要： A method detects electromigration in an electronic device. An integrated circuit, which is within an electronic device, is quiescented. An isolation power switch applies a test voltage from a field power source to a target voltage rail in the integrated circuit. An isolation power switch isolates the target voltage rail from the field power source. A voltage sensor coupled to the target voltage rail measures a field voltage decay rate for the target voltage rail. A voltage record comparator logic within the integrated circuit compares the field voltage decay rate to an initial voltage decay rate for the target voltage rail. In response to a difference between the field voltage decay rate and the initial voltage decay rate for the target voltage rail exceeding a predetermined limit, a signal is sent to an alarm associated with the electronic device.
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公开(公告)号：US09857416B2
公开(公告)日：2018-01-02
申请号：US15054464
申请日：2016-02-26
CPC分类号： G01R31/025 , G01R31/024 , G01R31/2851 , G01R31/2856 , G01R31/2858 , G01R31/3008
摘要： A method detects electromigration in a field replaceable unit. An integrated circuit, which is within a field replaceable unit (FRU) in an electronic device, is quiescented. An isolation power switch applies a test voltage from a field power source to a target voltage rail in the integrated circuit. An isolation power switch isolates the target voltage rail from the field power source. A voltage sensor coupled to the target voltage rail measures a field voltage decay rate for the target voltage rail. A voltage record comparator logic within the integrated circuit compares the field voltage decay rate to an initial voltage decay rate for the target voltage rail. In response to a difference between the field voltage decay rate and the initial voltage decay rate for the target voltage rail exceeding a predetermined limit, a signal is sent to an output device.
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公开(公告)号：US09762212B1
公开(公告)日：2017-09-12
申请号：US15245896
申请日：2016-08-24
CPC分类号： H03K3/0372 , G06F1/12 , G06F13/1673 , G06F13/4243 , H03K19/20
摘要： Aspects include a computer-implemented method for initializing scannable and non-scannable latches from a clock buffer. The method includes receiving a clock signal; receiving control signals including a hold signal, a scan enable signal, and a non-scannable latch force signal; responsive to receiving a low input from the hold signal and the scan enable signal, outputting a high signal from a functional clock port on a next cycle; responsive to receiving a high input from the scan enable signal and a low input from the hold signal, outputting a high slave latch scan clock signal on the next cycle; responsive to receiving a high input from the hold signal and the scan enable signal, outputting a high master latch clock signal on the next clock cycle; and responsive to receiving a high input from the non-scannable latch force signal, outputting a low master latch clock signal on a current cycle.
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公开(公告)号：US09753076B2
公开(公告)日：2017-09-05
申请号：US15008802
申请日：2016-01-28
CPC分类号： G01R31/025 , G01R31/024 , G01R31/2851 , G01R31/2856 , G01R31/2858 , G01R31/3008
摘要： An integrated circuit is configured to detect current leakage that results from electromigration in the integrated circuit. An isolation power switch selectively connects a target voltage rail in the integrated circuit to a power source. A voltage memory stores a record of an initial voltage decay rate for the target voltage rail while isolated from a manufacturer's power source. A voltage record comparator logic compares the initial voltage decay rate to a field voltage decay rate for the target voltage rail when isolated from a field power source. An output device indicates that a difference between the initial voltage decay rate and the field voltage decay rate for the target voltage rail exceeds a predefined limit, where the difference is a result of current leakage caused by electromigration in the integrated circuit.
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公开(公告)号：US20170219648A1
公开(公告)日：2017-08-03
申请号：US15054464
申请日：2016-02-26
IPC分类号： G01R31/28
CPC分类号： G01R31/025 , G01R31/024 , G01R31/2851 , G01R31/2856 , G01R31/2858 , G01R31/3008
摘要： A method detects electromigration in a field replaceable unit. An integrated circuit, which is within a field replaceable unit (FRU) in an electronic device, is quiescented. An isolation power switch applies a test voltage from a field power source to a target voltage rail in the integrated circuit. An isolation power switch isolates the target voltage rail from the field power source. A voltage sensor coupled to the target voltage rail measures a field voltage decay rate for the target voltage rail. A voltage record comparator logic within the integrated circuit compares the field voltage decay rate to an initial voltage decay rate for the target voltage rail. In response to a difference between the field voltage decay rate and the initial voltage decay rate for the target voltage rail exceeding a predetermined limit, a signal is sent to an output device.
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公开(公告)号：US20150262711A1
公开(公告)日：2015-09-17
申请号：US14205724
申请日：2014-03-12
发明人： Luiz C. Alves , William J. Clarke , Christopher R. Conklin , William V. Huott , Kevin W. Kark , Thomas J. Knips , K. Paul Muller
IPC分类号： G11C29/44
CPC分类号： G11C29/4401 , G11C29/08 , G11C29/12 , G11C29/24 , G11C29/44 , G11C29/50 , G11C29/785 , G11C2029/2602
摘要： Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.
摘要翻译： 实施例涉及芯片上未使用元件的内置测试。 一个方面包括在芯片上并行执行包括多个芯片元件的芯片元件，所述多个芯片元件包括多个有源元件，每个有源元件能够执行相应的功能，以及至少一个未被使用的元件被禁止执行相应的功能并被配置为选择性地 启用作为活动元件，相应活动元件的相应功能和至少一个未使用元件的内置自检（BIST）测试。 另一方面包括将输入测试图案输入到未使用的元件。 另一方面包括基于来自未使用元件的输入测试图案接收输出测试图案。 另一方面包括将输入测试模式与输出测试模式进行比较。 另一方面包括基于比较来确定未使用的元件是否通过或失败测试。
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