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公开(公告)号：US10896081B2
公开(公告)日：2021-01-19
申请号：US16219252
申请日：2018-12-13
摘要： A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.
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公开(公告)号：US10332591B2
公开(公告)日：2019-06-25
申请号：US15902065
申请日：2018-02-22
发明人： William V. Huott , Chandrasekharan Kothandaraman , Adam J. McPadden , Uma Srinivasan , Stephen Wu
IPC分类号： G11C11/419 , G11C29/12 , G11C29/50
摘要： Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.
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公开(公告)号：US10163493B2
公开(公告)日：2018-12-25
申请号：US15589071
申请日：2017-05-08
发明人： William V. Huott , Chandrasekharan Kothandaraman , Adam J. McPadden , Uma Srinivasan , Stephen Wu
IPC分类号： G11C11/419 , G11C29/50 , G11C29/12
摘要： Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.
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4.发明申请公开(公告)号：US20180089126A1
公开(公告)日：2018-03-29
申请号：US15278665
申请日：2016-09-28
发明人： David D. Cadigan , Samuel R. Connor , Michael A. Cracraft , William V. Huott , Adam J. McPadden , Anuwat Saetow , Gary A. Tressler
CPC分类号： G06F13/4022 , G06F1/3296 , G06F13/4286
摘要： An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable manner. The control may allow a maximum data rate to be achieved. In one embodiment, an algorithm used to determine phase change data may be handled by a feedback loop and may be dynamically adjusted. The system may detect noise on rails and critical signals for logging in call home data. The system may maintain a database of settings as a function of a workload. The system may be used in the field as the workload changes to determine that a signal has reached a first threshold. In response to determining that the signal has reached the first threshold, an alert is initiated. A system may determine that the signal has reached a second threshold. In response to determining that the signal has reached the second threshold, the signal may be coupled to logic circuitry.
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公开(公告)号：US09746516B2
公开(公告)日：2017-08-29
申请号：US15139499
申请日：2016-04-27
IPC分类号： G01R31/3177 , G01R31/28 , G01R31/3185 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/318541 , G01R31/318544
摘要： A failing latch is identified on a chip including a plurality of latches with the failing latch receiving data propagated from a first set of test input latches. A diagnostic set of latches is determined which includes the failing latch and a set of related latches. The set of related latches each receives data propagated from at least one test input latch from the first set of test input latches. The set of related latches is identified from a related latches table. One or more tests are performed on the chip and test output data is collected from the diagnostic set of latches. The related latches table is created by tracing from a target latch.
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公开(公告)号：US09627012B1
公开(公告)日：2017-04-18
申请号：US15197271
申请日：2016-06-29
发明人： William V. Huott , Norman K. James , Pradip Patel , Daniel Rodko
CPC分类号： G11C19/28
摘要： Aspects include a computer-implemented method for scanning data into a shift register. The method includes receiving, by a circuit, a data signal, wherein the data signal propagates in a first direction; and receiving, by the circuit, a clock signal, wherein the clock signal propagates in a second direction, wherein the second direction is in a reverse direction of the first direction.
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公开(公告)号：US09285423B2
公开(公告)日：2016-03-15
申请号：US14107596
申请日：2013-12-16
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/318541 , G01R31/318544
摘要： A system and method of a test structure for testing a chip is disclosed. The system may include a scan channel comprising a plurality of scannable latches. The scan channel may be configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip. The system may further include, a storage configured to store unmodified a selected bit of the scan channel during a scan out of the scan channel.
摘要翻译： 公开了一种用于测试芯片的测试结构的系统和方法。 该系统可以包括包括多个可扫描闩锁的扫描通道。 扫描通道可以被配置为扫描输入数据以应用于芯片上的逻辑电路，并进一步被配置为从芯片上的逻辑电路接收输出。 该系统还可以包括：被配置为在扫描出扫描通道之前将未修改的扫描通道的选定位存储的存储器。
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公开(公告)号：US20150168490A1
公开(公告)日：2015-06-18
申请号：US14107596
申请日：2013-12-16
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318541 , G01R31/318544
摘要： A system and method of a test structure for testing a chip is disclosed. The system may include a scan channel comprising a plurality of scannable latches. The scan channel may be configured to scan input data to apply to logic circuits on a chip and further configured to receive outputs from logic circuits on the chip. The system may further include, a storage configured to store unmodified a selected bit of the scan channel during a scan out of the scan channel.
摘要翻译： 公开了一种用于测试芯片的测试结构的系统和方法。 该系统可以包括包括多个可扫描闩锁的扫描通道。 扫描通道可以被配置为扫描输入数据以应用于芯片上的逻辑电路，并进一步被配置为从芯片上的逻辑电路接收输出。 该系统还可以包括：被配置为在扫描出扫描通道之前将未修改的扫描通道的选定位存储的存储器。
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公开(公告)号：US09021328B2
公开(公告)日：2015-04-28
申请号：US13741602
申请日：2013-01-15
发明人： William V. Huott , Kevin W. Kark , John G. Massey , K. Paul Muller , David L. Rude , David S. Wolpert
CPC分类号： H03M13/2909
摘要： A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction. The method further includes adding a product code to the array, the product code including applying the second error control mechanism to a plurality of bits of the first error control mechanism.
摘要翻译： 向多个寄存器组中添加错误检测或纠错的错误检测的方法包括将多个寄存器组分组成阵列。 该方法还包括在第一方向上向阵列添加第一错误控制机制，并在第二方向向阵列添加第二错误控制机制。 该方法还包括向阵列添加产品代码，产品代码包括将第二错误控制机制应用于第一错误控制机构的多个位。
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公开(公告)号：US20140208184A1
公开(公告)日：2014-07-24
申请号：US13747896
申请日：2013-01-23
发明人： William V. Huott , Kevin W. Kark , John G. Massey , K. Paul Muller , David L. Rude , David S. Wolpert
IPC分类号： H03M13/15
CPC分类号： H03M13/2909 , G06F11/1048 , H03M13/05 , H03M13/29
摘要： A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.
摘要翻译： 用于向存储单元阵列提供错误检测和/或校正的方法包括确定存储单元的敏感方向和不敏感方向，并且向不敏感方向的存储单元阵列添加第一误差控制机制。 该方法还包括向灵敏方向的存储单元阵列添加第二错误控制机制。 第二误差控制机构具有比第一误差控制机构更高的汉明距离。
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