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公开(公告)号：US11119676B2
公开(公告)日：2021-09-14
申请号：US16677740
申请日：2019-11-08
摘要： Disclosed is a computer implemented method to mark data as persistent using spare bits. The method includes receiving, by a memory system, a set of data, wherein the set of data includes a subset of meta-bits, and the set of data is received as a plurality of transfers, and wherein the memory system includes a first rank and a second rank. The method also includes decoding, by a decoder, the subset of meta-bits, wherein the subset of meta-bits are configured to indicate the set of data is important. The method further includes storing, based on the decoding, the set of data in a persistent storage medium.
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公开(公告)号：US10949295B2
公开(公告)日：2021-03-16
申请号：US16219166
申请日：2018-12-13
摘要： A method and a circuit for implementing dynamic single event upset (SEU) detection and correction, and a design structure on which the subject circuit resides are provided. The circuit implements detection, correction and scrubbing of unwanted state changes due to SEUs, noise or other event in semiconductor circuits. The circuit includes a plurality of L1 L2 latches connected in a chain, each L1 L2 latch includes an L1 latch and an L2 latch with the L2 latch having a connected output monitored for a flip. A single L2 detect circuit exclusive OR (XOR) is connected to each L2 latch. An L2 detect circuit XOR tree includes an input connected to a true output of a respective L2 latch in the chain. An L2 clock (LCK) trigger circuit is connected to an output of the L2 detect circuit XOR tree and is shared across each of the plurality of L1 L2 latches for correcting bit flip errors.
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公开(公告)号：US10585672B2
公开(公告)日：2020-03-10
申请号：US15099047
申请日：2016-04-14
发明人： David D. Cadigan , Stephen P. Glancy , William V. Huott , Kyu-hyoun Kim , Adam J. McPadden , Anuwat Saetow , Gary A. Tressler
IPC分类号： G06F9/44 , G06F1/04 , G06F9/4401
摘要： A computer-implemented method for command-address-control calibration of a memory device includes starting, via a processor, a controller clock for the memory device, releasing, via the processor, a reset on the memory device, running, via the processor, a calibration pattern for calibrating the memory device by placing the memory device in calibration mode, where the calibration pattern is initiated prior to an initialization of the memory device, calibrating, via the processor, the memory device with a calibration setting based on the calibration pattern, and initializing the memory device based on the calibration setting.
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公开(公告)号：US10229738B2
公开(公告)日：2019-03-12
申请号：US15496114
申请日：2017-04-25
IPC分类号： G11C14/00 , G11C13/00 , G11C11/419 , G11C29/12
摘要： Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.
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公开(公告)号：US09899067B2
公开(公告)日：2018-02-20
申请号：US15406655
申请日：2017-01-13
发明人： John S. Bialas, Jr. , David D. Cadigan , Stephen P. Glancy , Warren E. Maule , Gary A. Van Huben
CPC分类号： G11C7/22 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C11/401 , G11C11/4076 , G11C11/409 , G11C11/4093 , G11C29/50012 , G11C2029/5004 , G11C2207/2254
摘要： A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.
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公开(公告)号：US11520659B2
公开(公告)日：2022-12-06
申请号：US16741017
申请日：2020-01-13
发明人： Patrick James Meaney , Glenn David Gilda , David D. Cadigan , Christian Jacobi , Lawrence Jones , Stephen J. Powell
摘要： A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.
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公开(公告)号：US10896081B2
公开(公告)日：2021-01-19
申请号：US16219252
申请日：2018-12-13
摘要： A method and a circuit for implementing single event upset (SEU) parity detection, and a design structure on which the subject circuit resides are provided. The circuit implements detection of unwanted state changes due to SEUs, noise or other event in a latch having a default state of zero. The latch includes an L1 latch and an L2 latch with the L2 latch having the connected output and is used and monitored for a flip. A pair of series-connected field effect transistors (FETs) is connected between a drive input of a parity control circuit and ground potential. An inverted output of the L1 latch and a true output of the L2 latch is applied to a respective gate of the pair of series-connected FETs.
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8.发明申请公开(公告)号：US20180089126A1
公开(公告)日：2018-03-29
申请号：US15278665
申请日：2016-09-28
发明人： David D. Cadigan , Samuel R. Connor , Michael A. Cracraft , William V. Huott , Adam J. McPadden , Anuwat Saetow , Gary A. Tressler
CPC分类号： G06F13/4022 , G06F1/3296 , G06F13/4286
摘要： An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable manner. The control may allow a maximum data rate to be achieved. In one embodiment, an algorithm used to determine phase change data may be handled by a feedback loop and may be dynamically adjusted. The system may detect noise on rails and critical signals for logging in call home data. The system may maintain a database of settings as a function of a workload. The system may be used in the field as the workload changes to determine that a signal has reached a first threshold. In response to determining that the signal has reached the first threshold, an alert is initiated. A system may determine that the signal has reached a second threshold. In response to determining that the signal has reached the second threshold, the signal may be coupled to logic circuitry.
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公开(公告)号：US20170154660A1
公开(公告)日：2017-06-01
申请号：US15406655
申请日：2017-01-13
发明人： John S. Bialas, JR. , David D. Cadigan , Stephen P. Glancy , Warren E. Maule , Gary A. Van Huben
CPC分类号： G11C7/22 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C11/401 , G11C11/4076 , G11C11/409 , G11C11/4093 , G11C29/50012 , G11C2029/5004 , G11C2207/2254
摘要： A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.
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公开(公告)号：US09620184B1
公开(公告)日：2017-04-11
申请号：US14970798
申请日：2015-12-16
发明人： John S. Bialas, Jr. , David D. Cadigan , Stephen P. Glancy , Warren E. Maule , Gary A. Van Huben
CPC分类号： G11C7/22 , G11C5/147 , G11C7/1066 , G11C7/1093 , G11C7/14 , G11C11/4093 , G11C11/4099 , G11C29/021 , G11C29/023 , G11C29/025 , G11C29/028 , G11C2207/2254
摘要： A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.
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