公开(公告)号：US11798924B2

公开(公告)日：2023-10-24

申请号：US16902725

申请日：2020-06-16

Applicant: Infineon Technologies AG

Inventor： Kirill Trunov ,  Waltraud Eisenbeil ,  Frederick Groepper ,  Joerg Schadewald ,  Arthur Unrau ,  Ulrich Wilke

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/373 ,  H01L23/538 ,  H01L25/07

CPC classification number: H01L25/16 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/32227 ,  H01L2224/32507 ,  H01L2224/8381 ,  H01L2224/83815

Abstract: A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature.

公开(公告)号：US11652028B2

公开(公告)日：2023-05-16

申请号：US17160612

申请日：2021-01-28

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Carsten Ehlers ,  Arthur Unrau

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/08 ,  H01L23/14 ,  H01L23/31 ,  H01L23/492 ,  H01L23/00

CPC classification number: H01L23/49 ,  H01L21/4825 ,  H01L21/4875 ,  H01L23/08 ,  H01L23/14 ,  H01L23/3121 ,  H01L23/492 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83801

Abstract: A power semiconductor device includes a die carrier, a power semiconductor chip coupled to the die carrier by a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier by a second solder joint, and a sealing mechanically attaching the sleeve to the die carrier, the sealing being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the sealing does not cover the power semiconductor chip.

公开(公告)号：US11538694B2

公开(公告)日：2022-12-27

申请号：US16951633

申请日：2020-11-18

Applicant: Infineon Technologies AG

Inventor： Achim Muecke ,  Arthur Unrau

IPC: H01L21/48 ,  H01L23/492 ,  H01L25/00 ,  H01L25/07 ,  H01L25/18

Abstract: A method of manufacturing a module is disclosed. In one example, the method comprises providing at least one solder body with a base portion and an elevated edge extending along at least part of a circumference of the base portion. At least one carrier, on which at least one electronic component is mounted, is placed in the at least one solder body so that the at least one carrier is positioned on the base portion and is spatially confined by the elevated edge.

公开(公告)号：US20220238478A1

公开(公告)日：2022-07-28

申请号：US17582832

申请日：2022-01-24

Applicant: Infineon Technologies AG

Inventor： Arthur Unrau ,  Szabolcs Barna ,  Tobias Buehner ,  Norbert Kanvasi

IPC: H01L23/00 ,  B23K1/00 ,  B23K3/08

Abstract: An arrangement includes a chamber, a heating element arranged in the chamber, wherein the heating element, when a first connection partner with a pre-connection layer formed thereon is arranged in the chamber, is configured to heat the first connection partner and the pre-connection layer, thereby melting the pre-connection layer, and a cooling trap. During the process of heating the first connection partner with the pre-connection layer formed thereon, the cooling trap has a temperature that is lower than the temperature of all other components of or in the chamber such that liquid evaporating from the pre-connection layer is attracted by and condenses on the cooling trap.

公开(公告)号：US20210391310A1

公开(公告)日：2021-12-16

申请号：US16902725

申请日：2020-06-16

Applicant: Infineon Technologies AG

Inventor： Kirill Trunov ,  Waltraud Eisenbeil ,  Frederick Groepper ,  Joerg Schadewald ,  Arthur Unrau ,  Ulrich Wilke

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A batch soldering method includes providing a first passive device, arranging the first passive device on a first metal region of a substrate with a region of first solder material between the first passive device and the substrate, providing a semiconductor die, arranging the semiconductor die on a second metal region of the substrate with a region of second solder material between the semiconductor die and the substrate, and performing a common soldering step that simultaneously forms a first soldered joint from the region of first solder material and forms a second soldered joint from the region of second solder material. The common soldering step is performed at a soldering temperature such that one or more intermetallic phases form within the second soldered joint, each of the one or more intermetallic phases having a melting point above the second solder material and the soldering temperature.