公开(公告)号：US20200027752A1

公开(公告)日：2020-01-23

申请号：US16588447

申请日：2019-09-30

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Guido Boenig ,  Niels Oeschler ,  Christian Stahlhut

IPC: H01L21/48 ,  H01L23/373 ,  H01L23/00 ,  H01L23/492

Abstract: A method includes placing a substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the substrate, thereby pressing the substrate onto the first curved surface and bending the substrate, and removing the bended substrate from the first bending tool.

公开(公告)号：US10600658B2

公开(公告)日：2020-03-24

申请号：US16588447

申请日：2019-09-30

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Guido Boenig ,  Niels Oeschler ,  Christian Stahlhut

IPC: H01L21/48 ,  H01L23/373 ,  H01L23/492 ,  H01L23/00

Abstract: A method includes placing a substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the substrate, thereby pressing the substrate onto the first curved surface and bending the substrate, and removing the bended substrate from the first bending tool.

公开(公告)号：US11652028B2

公开(公告)日：2023-05-16

申请号：US17160612

申请日：2021-01-28

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Carsten Ehlers ,  Arthur Unrau

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/08 ,  H01L23/14 ,  H01L23/31 ,  H01L23/492 ,  H01L23/00

CPC classification number: H01L23/49 ,  H01L21/4825 ,  H01L21/4875 ,  H01L23/08 ,  H01L23/14 ,  H01L23/3121 ,  H01L23/492 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83801

Abstract: A power semiconductor device includes a die carrier, a power semiconductor chip coupled to the die carrier by a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier by a second solder joint, and a sealing mechanically attaching the sleeve to the die carrier, the sealing being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the sealing does not cover the power semiconductor chip.

公开(公告)号：US20220278026A1

公开(公告)日：2022-09-01

申请号：US17680409

申请日：2022-02-25

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Tobias Buehner ,  Alexander Ciliox ,  Peter Lahl

IPC: H01L23/492 ,  H01L21/48 ,  H01L23/15 ,  H01L23/00

Abstract: A method for fabricating a substrate comprising a solder stop structure comprises providing a substrate configured to carry a surface mounted device, the substrate comprising a ceramic layer and a metallization arranged on the ceramic layer, wherein the metallization comprises a base metal layer and a noble metal layer covering the base metal layer, and generating an oxidation structure on the metallization, wherein the oxidation structure divides the metallization into a first part and a second part, and wherein the oxidation structure is configured to act as a solder stop, wherein generating the oxidation structure comprises partially removing the noble metal layer.

公开(公告)号：US20210242111A1

公开(公告)日：2021-08-05

申请号：US17160612

申请日：2021-01-28

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Carsten Ehlers ,  Arthur Unrau

IPC: H01L23/49 ,  H01L23/31 ,  H01L23/14 ,  H01L23/492 ,  H01L23/08 ,  H01L23/00 ,  H01L21/48

Abstract: A power semiconductor device includes a die carrier, a power semiconductor chip coupled to the die carrier by a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier by a second solder joint, and a sealing mechanically attaching the sleeve to the die carrier, the sealing being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the sealing does not cover the power semiconductor chip.

公开(公告)号：US10475668B2

公开(公告)日：2019-11-12

申请号：US16021619

申请日：2018-06-28

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Guido Boenig ,  Niels Oeschler ,  Christian Stahlhut

IPC: H01L21/48 ,  H01L23/373 ,  H01L23/00 ,  H01L23/492

Abstract: A method includes placing a semiconductor substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the semiconductor substrate, thereby pressing the semiconductor substrate onto the first curved surface and bending the semiconductor substrate, and removing the bended semiconductor substrate from the first bending tool.

公开(公告)号：US20190006193A1

公开(公告)日：2019-01-03

申请号：US16021619

申请日：2018-06-28

Applicant: Infineon Technologies AG

Inventor： Andre Wedi ,  Guido Boenig ,  Niels Oeschler ,  Christian Stahlhut

IPC: H01L21/48 ,  H01L23/373 ,  H01L23/492

CPC classification number: H01L21/4878 ,  H01L23/3735 ,  H01L23/492 ,  H01L24/75 ,  H01L2224/79315 ,  H01L2924/3511

Abstract: A method includes placing a semiconductor substrate on a first curved surface of a first bending tool, using a second bending tool with a second surface to apply pressure to the semiconductor substrate, thereby pressing the semiconductor substrate onto the first curved surface and bending the semiconductor substrate, and removing the bended semiconductor substrate from the first bending tool.