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11.发明公开公开(公告)号：US20240122075A1
公开(公告)日：2024-04-11
申请号：US18264903
申请日：2021-03-19
发明人： Guozhong XING , Long LIU , Di WANG , Huai LIN , Yan WANG , Xiaoxin XU , Ming LIU
摘要： An activation function generator based on a magnetic domain wall driven magnetic tunnel junction and a method for manufacturing the same are provided, including: a spin orbit coupling layer configured to generate a spin orbit torque; a ferromagnetic free layer formed on the spin orbit coupling layer and configured to provide a magnetic domain wall motion racetrack; a nonmagnetic barrier layer formed on the ferromagnetic free layer; a ferromagnetic reference layer formed on the nonmagnetic barrier layer; a top electrode formed on the ferromagnetic reference layer; antiferromagnetic pinning layers formed on two ends of the ferromagnetic free layer; a left electrode and a right electrode respectively formed at two positions on the antiferromagnetic pinning layers.
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公开(公告)号：US20230280978A1
公开(公告)日：2023-09-07
申请号：US18005756
申请日：2021-01-21
发明人： Guozhong XING , Huai LIN , Di WANG , Long LIU , Feng ZHANG , Changqing XIE , Ling LI , Ming LIU
CPC分类号： G06F7/57 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Provided are a spin orbit torque magnetic random access memory cell, a spin orbit torque magnetic random access memory array and a method for calculating a Hamming distance, wherein the spin orbit torque magnetic random access memory cell includes a magnetic tunnel junction; a first transistor, a drain terminal of the first transistor being connected to a bottom of the magnetic tunnel junction; and a second transistor, a drain terminal of the second transistor being connected to a top of the magnetic tunnel junction.
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公开(公告)号：US20230267990A1
公开(公告)日：2023-08-24
申请号：US18005101
申请日：2020-08-24
发明人： Qing LUO , Bing CHEN , Hangbing LV , Ming LIU , Cheng LU
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4094 , H03K19/017
CPC分类号： G11C11/4096 , G11C11/4085 , G11C11/4094 , H03K19/01742
摘要： Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.
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公开(公告)号：US20230245691A1
公开(公告)日：2023-08-03
申请号：US18004968
申请日：2020-07-20
CPC分类号： G11C11/161 , H10B61/22 , H10N50/20 , H10N50/80 , H10N50/85 , H10N50/01 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Provided is a cache memory, including: a first field-effect transistor, a field-like spin torque layer underneath a magnetic tunnel junction, an electrode, and a second field-effect transistor sequentially arranged and connected; wherein the first field-effect transistor is configured to provide a writing current and to control the on-off of the writing current through a gate electrode; the field-like spin torque layer is configured to generate field-like spin torques for switching a first ferromagnetic layer of the magnetic tunnel junction; the magnetic tunnel junction includes a first ferromagnetic layer, a tunneling layer, a second ferromagnetic layer and a pinning layer arranged sequentially; the electrode is configured to connect the cache memory with the second field-effect transistor; and the second field-effect transistor is configured to control the on-off of the second field-effect transistor through the gate electrode to read the resistive state of the magnetic tunnel junction.
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公开(公告)号：US20210165027A1
公开(公告)日：2021-06-03
申请号：US16065582
申请日：2015-12-25
发明人： Guangwei XU , Zhiheng HAN , Wei WANG , Congyan LU , Lingfei WANG , Ling LI , Ming LIU
摘要： A method for obtaining a contact resistance of a planar device includes: obtaining a contact resistance of a planar device by using a potential measurement method, in the measurement of the surface potential distribution, the planar device is in a state of current flowing, a certain voltage drop is formed at a junction area of the device; extracting the voltage drop measured through the Kelvin microscope by using a linear fitting method; and dividing the measured voltage drop by the current flowing through the device, thereby accurately calculating the magnitude of the contact resistance at the junction area of the planar device. With the present invention, the contact resistance of the planar device can be precisely measured, which is suitable for the contact resistance measurement experiments of devices such as thin film transistors and diodes. The invention has the advantages of reasonable theory, accurate result, simple and easy operation, and is favorable for optimizing the device performance and establishing a complete electrical model of the device.
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公开(公告)号：US20210013404A1
公开(公告)日：2021-01-14
申请号：US16767091
申请日：2018-03-28
发明人： Qing LUO , Hangbing LV , Ming LIU
IPC分类号： H01L45/00
摘要： The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.
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17.发明申请公开(公告)号：US20190115529A1
公开(公告)日：2019-04-18
申请号：US16085400
申请日：2016-03-18
发明人： Ming LIU , Qing LUO , Xiaoxin XU , Hangbing LV , Shibing LONG , Qi LIU
摘要： A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400° C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.
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18.发明申请公开(公告)号：US20160123944A1
公开(公告)日：2016-05-05
申请号：US14896342
申请日：2013-06-05
发明人： Dongmei LI , Shuang ZHAN , Shengfa LIANG , Xin CHEN , Changqing XIE , Ming LIU
IPC分类号： G01N33/00
CPC分类号： G01N33/0036 , G01N27/00 , G01N27/12 , G01N33/0037
摘要： A method for manufacturing an NO2 gas sensor for detection at room temperature comprises: manufacturing a metal electrode on a surface of a flexible substrate; manufacturing an SWCNTs/SnO2 sensitive film; and bonding the SWCNTs/SnO2 sensitive film with a portion of the surface of the flexible substrate with the metal electrode, so as to form the NO2 gas sensor for detection at room temperature. The present disclosure solves the problems of the poor adhesion between the sensitive material and the flexible substrate, and a non-uniform distribution, and achieves the purposes of secure bonding between the sensitive material and the flexible substrate, and uniform distribution.
摘要翻译： 一种用于在室温下检测的NO 2气体传感器的制造方法包括：在柔性基板的表面上制造金属电极; 制造SWCNTs / SnO2敏感膜; 并将SWCNTs / SnO2敏感膜与柔性基板表面的一部分与金属电极接合，以便形成用于在室温下检测的NO 2气体传感器。 本公开解决了敏感材料与柔性基板之间的粘合性差，分布不均匀的问题，并且实现了敏感材料与柔性基板之间的牢固结合的目的，并且均匀分布。
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公开(公告)号：US20230337548A1
公开(公告)日：2023-10-19
申请号：US18042249
申请日：2020-08-20
发明人： Guozhong XING , Huai LIN , Yu LIU , Peiwen ZHANG , Changqing XIE , Ling LI , Ming LIU
CPC分类号： H10N50/20 , G11C11/161 , H10B61/10 , H10N50/85 , G06F7/501 , G11C11/1673 , G11C11/1675
摘要： An SOT-driven field-free switching MRAM and an array thereof. From top to bottom, the SOT-MRAM sequentially includes: a selector (1) configured to turn on or turn off the SOT-MRAM under an action of an external voltage; a magnetic tunnel junction (2), including a ferromagnetic reference layer, a tunneling layer and a ferromagnetic free layer arranged sequentially from top to bottom; and a spin-orbit coupling layer (3) made of one or more selected from heavy metal, doped heavy metal, heavy metal alloy, metal oxide, dual heavy metal layers, semiconductor material, two-dimensional semi-metal material and anti-ferromagnetic material. The spin-orbit coupling layer is configured to generate an in-plane effective field in the ferromagnetic free layer by using the interlayer exchange coupling effect and generate spin-orbit torques by using the spin Hall effect, so as to perform a deterministic data storage in the magnetic tunnel junction (2).
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公开(公告)号：US20230197152A1
公开(公告)日：2023-06-22
申请号：US17996194
申请日：2020-04-14
发明人： Hangbing LV , Jianguo YANG , Xiaoxin XU , Ming LIU
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/003 , G11C13/0038 , G11C13/0026 , G11C13/0028 , G11C2213/79
摘要： Provided are a memory cell structure, a memory array structure, and a voltage biasing method. The memory cell structure includes: a substrate layer, a well layer and a transistor. The substrate layer is configured to support the memory cell structure; the well layer is embedded in the substrate layer, an upper surface of the well layer is flush with an upper surface of the substrate layer, and a transistor is arranged on the well layer. In the present disclosure, a deep well bias is performed on the memory cell structure, so that the well voltage of the memory cell may be individually biased to a specific voltage, and in combination with the redesigned memory cell array structure, the applied programming voltage mostly falls on the memory cell structure. This reduces the programming voltage of the memory cell, and avoids a breakdown of the selecting transistor due to an excessively large voltage, thereby ensuring a great reliability of the device and a higher efficiency within the area of the memory cell array structure.
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