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    VARIABLE IN-PLANE SIGNAL TO GROUND REFERENCE CONFIGURATIONS
    11.
    发明申请
    VARIABLE IN-PLANE SIGNAL TO GROUND REFERENCE CONFIGURATIONS 审中-公开

    公开(公告)号：US20200312759A1

    公开(公告)日：2020-10-01

    申请号：US16366034

    申请日：2019-03-27

    Applicant: Intel Corporation

    Inventor： Andrew COLLINS ,  Arghya SAIN

    IPC: H01L23/498 ,  H01L23/66

    Abstract: Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.

    THICK AND THIN TRACES IN A BRIDGE WITH A GLASS CORE
    12.
    发明申请
    THICK AND THIN TRACES IN A BRIDGE WITH A GLASS CORE 有权

    公开(公告)号：US20230100576A1

    公开(公告)日：2023-03-30

    申请号：US17478450

    申请日：2021-09-17

    Applicant: Intel Corporation

    Inventor： Andrew COLLINS ,  Srinivas V. PIETAMBARAM ,  Jianyong XIE ,  Krishna Vasanth VALAVALA

    IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/42

    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to bridges having a glass core, where the bridges may include one or more thick traces and one or more thin traces, where the thin traces are layered closer to a surface of the glass core, and the thick traces are layered further away from the glass core. During operation, the thin traces may be used to transmit signals between the coupled dies, and the thick traces may be used to transmit power between the coupled dies. During manufacture, the rigidity and highly planner surface of the glass core may enable thinner traces closer to the surface of the glass core to be placed with greater precision resulting in increased overall quality and robustness of transmitted signals. Other embodiments may be described and/or claimed.

    PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE
    14.
    发明申请
    PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE 审中-公开

    公开(公告)号：US20200235051A1

    公开(公告)日：2020-07-23

    申请号：US16839393

    申请日：2020-04-03

    Applicant: Intel Corporation

    Inventor： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

    IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00

    Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

    PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE
    19.
    发明申请
    PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE 有权

    公开(公告)号：US20220148968A1

    公开(公告)日：2022-05-12

    申请号：US17585082

    申请日：2022-01-26

    Applicant: Intel Corporation

    Inventor： Andrew COLLINS ,  Bharat P. PENMECHA ,  Rajasekaran SWAMINATHAN ,  Ram VISWANATH

    IPC: H01L23/528 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: Various embodiments relate to a semiconductor package. The semiconductor package includes a first die. The first die includes a first bridge interconnect region. The semiconductor package further includes a second die. The second die includes a second bridge interconnect region. The semiconductor package includes a bridge die. The bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. In the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. Additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. An average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

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