公开(公告)号：US20180331003A1

公开(公告)日：2018-11-15

申请号：US15776755

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Adel A. ELSHERBINI ,  Mihir K. ROY ,  Aleksandar ALEKSOV ,  Yidnekachew S. MEKONNEN ,  Javier SOTO GONZALEZ ,  Feras EID ,  Suddhasattwa NAD ,  Meizi JIAO

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/12 ,  H01L21/486 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US20230343714A1

公开(公告)日：2023-10-26

申请号：US18216989

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Mathew J. MANUSHAROW ,  Jonathan ROSENFELD

IPC: H01L23/538 ,  H01L23/64 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/642 ,  H01L23/49822 ,  H01L25/50 ,  H01L23/647 ,  H01L21/4857 ,  H01L25/065 ,  H01L25/0655 ,  H01L23/49816 ,  H01L23/5385 ,  H01L2224/16235 ,  H01L24/16

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

公开(公告)号：US20200066641A1

公开(公告)日：2020-02-27

申请号：US16305012

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Richard J. DISCHLER ,  Jeff C. MORRISS ,  Zhiguo QIAN ,  Wilfred GOMES ,  Yu Amos ZHANG ,  Ram S. VISWANATH ,  Rajasekaran SWAMINATHAN ,  Sriram SRINIVASAN ,  Yidnekachew S. MEKONNEN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Mathew J. MANUSHAROW

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L23/60

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.

公开(公告)号：US20200051916A1

公开(公告)日：2020-02-13

申请号：US16658866

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Debendra MALLIK ,  Mathew J. MANUSHAROW ,  Jianyong XIE

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.

公开(公告)号：US20240413089A1

公开(公告)日：2024-12-12

申请号：US18806287

申请日：2024-08-15

Applicant: Intel Corporation

Inventor： Mathew J. MANUSHAROW ,  Jonathan ROSENFELD

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.

公开(公告)号：US20220102261A1

公开(公告)日：2022-03-31

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew J. MANUSHAROW ,  Krishna BHARATH ,  William J. LAMBERT ,  Robert L. SANKMAN ,  Aleksandar ALEKSOV ,  Brandon M. RAWLINGS ,  Feras EID ,  Javier SOTO GONZALEZ ,  Meizi JIAO ,  Suddhasattwa NAD ,  Telesphor KAMGAING

IPC: H01L23/498 ,  H01F17/00 ,  H01F27/40 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01G4/33 ,  H01L21/48 ,  H01L23/66

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US20190164881A1

公开(公告)日：2019-05-30

申请号：US16264195

申请日：2019-01-31

Applicant: INTEL CORPORATION

Inventor： Mathew J. MANUSHAROW ,  Dustin P. WOOD ,  Debendra MALLIK

IPC: H01L23/50 ,  H01L23/00 ,  H01L23/522 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L23/50 ,  G06F17/5068 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/02 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02311 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/14133 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

公开(公告)号：US20180331035A1

公开(公告)日：2018-11-15

申请号：US15773896

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yu Amos ZHANG ,  Mathew J. MANUSHAROW ,  Kemal AYGUN ,  Mohiuddin MAZUMDER

IPC: H01L23/528 ,  H01L23/50 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H05K1/02 ,  H01R13/6471

Abstract: A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.

公开(公告)号：US20180226310A1

公开(公告)日：2018-08-09

申请号：US15748138

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Feras EID ,  Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Yidnekachew MEKONNEN ,  Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Aleksandar ALEKSOV ,  Nathan FRITZ

IPC: H01L23/14 ,  H01L21/48 ,  H01L23/473 ,  H01L23/538 ,  H01L23/492

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L21/4871 ,  H01L23/12 ,  H01L23/473 ,  H01L23/492 ,  H01L23/5389

Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.

公开(公告)号：US20170027062A1

公开(公告)日：2017-01-26

申请号：US15286276

申请日：2016-10-05

Applicant: Intel Corporation

Inventor： MIHIR K. ROY ,  Mathew J. MANUSHAROW

IPC: H05K3/10 ,  H05K3/30 ,  H05K1/16 ,  H05K3/22 ,  H05K3/40

CPC classification number: H05K3/10 ,  H01B3/485 ,  H01B3/50 ,  H01B7/083 ,  H01F17/0006 ,  H05K1/0222 ,  H05K1/038 ,  H05K1/165 ,  H05K3/043 ,  H05K3/103 ,  H05K3/22 ,  H05K3/26 ,  H05K3/30 ,  H05K3/40 ,  H05K3/4046 ,  H05K2201/029 ,  H05K2201/097 ,  H05K2201/09809 ,  H05K2201/10287 ,  H05K2201/1081 ,  H05K2203/0228 ,  H05K2203/025 ,  H05K2203/1461 ,  H05K2203/175 ,  H05K2203/30

Abstract: A substrate package includes a woven fabric having electrically non-conductive strands woven between electrically conductive strands including wire strands, co-axial strands, and/or an inductor pattern of strands. The package may be formed by an inexpensive and high throughput process that first weaves the non-conductive strands (e.g., glass) between the conductive strands to form a circuit board pattern of conductive strands in a woven fabric. Next, the woven fabric is impregnated with a resin material to form an impregnated fabric, which is then cured to form a cured fabric. The upper and lower surfaces of the cured fabric are subsequently planarized. Planarizing segments and exposes ends of the wire, co-axial, and inductor pattern strands. Since the conductive strands were formed integrally within the planarized woven fabric, the substrate has a high mechanical stability and provides conductor strand based electrical components built in situ in the substrate package.

Abstract translation: 衬底封装包括织造织物，其具有在导电股线之间编织的非导电股线，包括线股，同轴股线和/或股线的电感器图案。 封装可以通过廉价且高通量的工艺来形成，该工艺首先在导电股线之间编织非导电股线（例如玻璃），以形成机织织物中导电股线的电路板图案。 接下来，用树脂材料浸渍织物以形成浸渍织物，然后将其固化以形成固化织物。 随后将固化的织物的上表面和下表面平坦化。 平面化节段并露出导线，同轴和电感图案线的端部。 由于导电丝线整体地形成在平面织造织物内，所以基底具有高的机械稳定性，并提供了在基底包装中原位构建的基于导线的电气部件。