-
公开(公告)号：US20200379917A1
公开(公告)日：2020-12-03
申请号：US16900424
申请日：2020-06-12
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Baiju V. Patel , Gur Hildesheim , Ron Rais , Andrew V. Anderson , Jason W. Brandt , David M. Durham , Barry E. Huntley , Raanan Sade , Ravi L. Sahita , Vedvyas Shanbhogue , Arumugam Thiyagarajah
IPC: G06F12/1009 , G06F12/14 , G06F9/455
Abstract: A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.
-
公开(公告)号：US20190018695A1
公开(公告)日：2019-01-17
申请号：US15978501
申请日：2018-05-14
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Dion Rodgers , Richard A. Uhlig , Lawrence O. Smith , Barry E. Huntley
Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a hardware processor including event circuit to recognize a virtualization event, and evaluation circuit to determine whether to transfer control of the apparatus from a child guest to a parent guest in response to the virtualization event, wherein the child guest and the parent guest each include a bit per virtualization event to indicate whether the parent guest is to gain control when the virtualization event occurs.
-
公开(公告)号：US09858167B2
公开(公告)日：2018-01-02
申请号：US14973238
申请日：2015-12-17
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Andrew V. Anderson , Richard A. Uhlig , David M. Durham , Ronak Singhal , Xiangbin Wu , Sailesh Kottapalli
CPC classification number: G06F11/3466 , G06F3/0604 , G06F3/0644 , G06F3/0673 , G06F11/3024 , G06F13/24
Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.
-
公开(公告)号：US09792222B2
公开(公告)日：2017-10-17
申请号：US14317571
申请日：2014-06-27
Applicant: Intel Corporation
Inventor： Ravi L. Sahita , Gilbert Neiger , David M. Durham , Vedvyas Shanbhogue , Michael Lemay , Ido Ouziel , Stanislav Shwartsman , Barry Huntley , Andrew V. Anderson
IPC: G06F12/10 , G06F12/14 , G06F9/455 , G06F12/1009
CPC classification number: G06F12/1009 , G06F9/45558 , G06F12/145 , G06F2009/45583 , G06F2009/45587 , G06F2212/651 , G06F2212/657 , Y02D10/13
Abstract: Systems and methods for validating virtual address translation. An example processing system comprises: a processing core to execute a first application associated with a first privilege level and a second application associated with a second privilege level, wherein a first set of privileges associated with the first privilege level includes a second set of privileges associated with the second privilege level; and an address validation component to validate, in view of an address translation data structure maintained by the first application, a mapping of a first address defined in a first address space of the second application to a second address defined in a second address space of the second application.
-
公开(公告)号：US20160019164A1
公开(公告)日：2016-01-21
申请号：US14867018
申请日：2015-09-28
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
CPC classification number: G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
-
Patent Agency Ranking
公开(公告)号：US20150100717A1
公开(公告)日：2015-04-09
申请号：US14569069
申请日：2014-12-12
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard UhligQ , Lawrence Smith, III , Scott D. Rodgers
IPC: G06F12/10
CPC classification number: G06F12/1483 , G06F9/45533 , G06F9/45558 , G06F12/109 , G06F2009/45583 , G06F2212/151 , G06F2212/152 , G06F2212/657
Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
Abstract translation: 一种处理器，其包括具有存储器虚拟化支持系统的处理器的虚拟化系统，以将参考映射到由虚拟机上可执行的客户机软件制成的客体物理存储器，该虚拟机器又可在主机上执行，其中处理器可操作为 引用主机的主机物理内存。
-
公开(公告)号：US20240220423A1
公开(公告)日：2024-07-04
申请号：US18147510
申请日：2022-12-28
Applicant: Intel Corporation
Inventor： Michael LeMay , David M. Durham , Salmin Sultana , Andrew V. Anderson , Hans Goran Liljestrand
CPC classification number: G06F12/1408 , H04L9/0819
Abstract: Techniques disclosed include selecting a first key identifier (ID) for a first compartment of a compartmentalized process of a computing system, the first compartment including first private data; assigning a first extended page table (EPT) having at least one memory address including the first key ID; encrypting the first private data with a first key associated with the first key ID; and storing the encrypted first private data in a memory starting at the at least one memory address of the first EPT.
-
公开(公告)号：US10713177B2
公开(公告)日：2020-07-14
申请号：US15260893
申请日：2016-09-09
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Baiju V. Patel , Gur Hildesheim , Ron Rais , Andrew V. Anderson , Jason W. Brandt , David M. Durham , Barry E. Huntley , Raanan Sade , Ravi L. Sahita , Vedvyas Shanbhogue , Arumugam Thiyagarajah
IPC: G06F12/1009 , G06F12/14 , G06F9/455
Abstract: A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.
-
公开(公告)号：US10599547B2
公开(公告)日：2020-03-24
申请号：US15827890
申请日：2017-11-30
Applicant: Intel Corporation
Inventor： Gilbert Neiger , Andrew V. Anderson , Richard A. Uhlig , David M. Durham , Ronak Singhal , Xiangbin Wu , Sailesh Kottapalli
Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.
-
公开(公告)号：US10180911B2
公开(公告)日：2019-01-15
申请号：US15620663
申请日：2017-06-12
Applicant: Intel Corporation
Inventor： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
IPC: G06F12/00 , G06F12/1027 , G06F12/0875 , G06F12/1045 , G06F9/455 , G06F12/02 , G06F12/1036 , G06F12/1009
Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
-
-
-
-
-
-
-
-
-
Search Results
62
records
(took 0.019 seconds)
