公开(公告)号：US09454218B2

公开(公告)日：2016-09-27

申请号：US14659253

申请日：2015-03-16

Applicant: Intel Corporation

Inventor： Jayakrishna Guddeti ,  Binata Bhattacharyya

IPC: G06F13/24 ,  G06F1/32 ,  G06F9/44

CPC classification number: G06F1/3287 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/4418 ,  G06F13/24 ,  Y02D10/24 ,  Y02D50/20

Abstract: An apparatus and method is described herein for providing an early wake scheme before spawning a new thread. An early wake indication may be provided an amount of time, which may include an amount of time to perform a demotion from a current power state to a lower power state that is closer to an active power state, before a new thread is to be spawned and executed on a processing element (e.g., core or thread). Upon encountering the spawn of the new thread, such as a helper thread, the processing element may further transition from the lower power state to an active power state. The new thread may be executed on the processing element without incurring the latency associated with execution of the new thread waiting for the demotion from the current power state to an active power state after the spawn of the new thread.

Abstract translation: 本文描述了一种在产生新线程之前提供早期唤醒方案的装置和方法。 早期的唤醒指示可以在新线程被产生之前提供一定的时间量，其可以包括执行从当前功率状态降级到更靠近有功功率状态的较低功率状态的时间量 并在处理元件（例如，核心或线程）上执行。 在遇到诸如辅助线程的新线程的产生时，处理元件可以进一步从较低功率状态转换到有功功率状态。 可以在处理元件上执行新线程，而不会在新线程的产生之后产生等待从当前功率状态到有功功率状态的新线程的执行相关联的延迟。

公开(公告)号：US11698673B2

公开(公告)日：2023-07-11

申请号：US17522294

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Binata Bhattacharyya ,  Paul S. Diefenbaugh

IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/3206 ,  G06F3/06 ,  G06F9/30 ,  G06F12/06

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F3/064 ,  G06F3/0625 ,  G06F9/30098 ,  G06F12/0607 ,  G06F3/0679

Abstract: Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

公开(公告)号：US11256318B2

公开(公告)日：2022-02-22

申请号：US16536408

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： Binata Bhattacharyya ,  Paul S. Diefenbaugh

IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/3206 ,  G06F3/06 ,  G06F9/30 ,  G06F12/06

Abstract: Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

公开(公告)号：US09893881B2

公开(公告)日：2018-02-13

申请号：US14753987

申请日：2015-06-29

Applicant: Intel Corporation

Inventor： Binata Bhattacharyya ,  Siddhartha Chhabra ,  Evgeny Zhyvov ,  Eugene M. Kishinevsky ,  Men Long

IPC: H04L9/06 ,  G06F21/72 ,  G06F21/76

CPC classification number: H04L9/0637 ,  G06F21/57 ,  G06F21/72 ,  G06F21/76 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125

Abstract: A processing or memory device may include a first encryption pipeline to encrypt and decrypt data with a first encryption mode and a second encryption pipeline to encrypt and decrypt data with a second encryption mode, wherein the first encryption pipeline and the second encryption pipeline share a single, shared pipeline for a majority of encryption and decryption operations performed by the first encryption pipeline and by the second encryption pipeline. A controller (and/or other logic) may direct selection of encrypted (or decrypted) data from the first and second encryption pipelines responsive to a region of memory to which a physical address of a memory request is directed. The result of the selection may result in bypassing encryption/decryption or encrypting/decrypting the data according to the first encryption mode or the second encryption mode. More than two encryption modes are envisioned.

公开(公告)号：US20170063532A1

公开(公告)日：2017-03-02

申请号：US14753987

申请日：2015-06-29

Applicant: Intel Corporation

Inventor： Binata Bhattacharyya ,  Siddhartha Chhabra ,  Evgeny Zhyvov ,  Eugene M. Kishinevsky ,  Men Long

IPC: H04L9/06 ,  G06F21/76 ,  G06F21/72

CPC classification number: H04L9/0637 ,  G06F21/57 ,  G06F21/72 ,  G06F21/76 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125

Abstract: A processing or memory device may include a first encryption pipeline to encrypt and decrypt data with a first encryption mode and a second encryption pipeline to encrypt and decrypt data with a second encryption mode, wherein the first encryption pipeline and the second encryption pipeline share a single, shared pipeline for a majority of encryption and decryption operations performed by the first encryption pipeline and by the second encryption pipeline. A controller (and/or other logic) may direct selection of encrypted (or decrypted) data from the first and second encryption pipelines responsive to a region of memory to which a physical address of a memory request is directed. The result of the selection may result in bypassing encryption/decryption or encrypting/decrypting the data according to the first encryption mode or the second encryption mode. More than two encryption modes are envisioned.

Abstract translation: 处理或存储设备可以包括用第一加密模式加密和解密数据的第一加密流水线和用第二加密模式对数据进行加密和解密的第二加密流水线，其中第一加密流水线和第二加密流水线共享一个 ，用于由第一加密流水线和第二加密流水线执行的大多数加密和解密操作的共享流水线。 响应于存储器请求的物理地址所针对的存储器区域，控制器（和/或其他逻辑）可以直接从第一和第二加密流水线中选择加密（或解密的）数据。 选择的结果可能导致绕过加密/解密或者根据第一加密模式或第二加密模式对数据进行加密/解密。 设想了两种以上的加密模式。

公开(公告)号：US09032126B2

公开(公告)日：2015-05-12

申请号：US14186630

申请日：2014-02-21

Applicant: Intel Corporation

Inventor： Jayakrishna Guddeti ,  Binata Bhattacharyya

IPC: G06F9/50 ,  G06F13/24 ,  G06F1/32 ,  G06F1/20

CPC classification number: G06F13/24 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/5038 ,  G06F9/5094 ,  Y02D10/22

Abstract: In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed.