公开(公告)号：US20180190540A1

公开(公告)日：2018-07-05

申请号：US15396469

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Jun Liu ,  Gordon A. Haller ,  Fei Wang ,  Wei Yeeng Ng ,  Wesley O. McKinsey ,  Zhiqiang Xie ,  Jeremy F. Adams ,  Hongbin Zhu ,  Jun Zhao ,  Mark A. Levan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

公开(公告)号：US20170170190A1

公开(公告)日：2017-06-15

申请号：US14970288

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/115 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  H01L21/768 ,  G11C16/08

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.