公开(公告)号：US11914438B2

公开(公告)日：2024-02-27

申请号：US17879576

申请日：2022-08-02

Applicant: Intel Corporation

Inventor： Marc Beuchat ,  Murali Ramadoss ,  Ankur Shah

IPC: G06F1/00 ,  G06F1/20 ,  G06T1/60 ,  G06T1/20

CPC classification number: G06F1/206 ,  G06T1/20 ,  G06T1/60

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240061582A1

公开(公告)日：2024-02-22

申请号：US17820356

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Marc Beuchat ,  Eric Samson ,  Josh Mastronarde

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0679

Abstract: Methods, systems and apparatuses provide for technology that detects an access to memory, wherein the memory is on a discrete graphics device that includes an accelerator, sets an idle hysteresis value of the memory to a first level if the access to the memory is associated with activity in the accelerator, and sets the idle hysteresis value of the memory to a second level if the access to the memory is not associated with the activity in the accelerator, wherein the second level is greater than the first level.

公开(公告)号：US20220382347A1

公开(公告)日：2022-12-01

申请号：US17879576

申请日：2022-08-02

Applicant: Intel Corporation

Inventor： Marc Beuchat ,  Murali Ramadoss ,  Ankur Shah

IPC: G06F1/20 ,  G06T1/60 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200260380A1

公开(公告)日：2020-08-13

申请号：US16783076

申请日：2020-02-05

Applicant: Intel Corporation

Inventor： Eric C. Samson ,  Murali Ramadoss ,  Marc Beuchat

IPC: H04W52/02 ,  G06F1/3234 ,  G06F1/324 ,  G06T1/20 ,  H04W52/18

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190204901A1

公开(公告)日：2019-07-04

申请号：US16230997

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Marc Beuchat

IPC: G06F1/3293 ,  G06F9/50 ,  G06F1/3228 ,  G06F1/329 ,  G06T1/20

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/5027 ,  G06F2209/509 ,  G06T1/20 ,  Y02D10/122 ,  Y02D10/24

Abstract: One or more system, apparatus, method, and computer readable media is described below for power management of one or more graphics processor resources. In some embodiments, a graphics processor context associated with an application an including power-related hardware configuration and control parameters is stored to memory. In some embodiments, graphics processor contexts are switched in and out as different application workloads are processed by resources of the graphics processor. In some embodiments, power-performance management algorithms are grouped and sequentially executed in ordered phases of a control loop to generate a compatible set of control parameter requests. Once finalized, the set is output as requests to graphics processor hardware and/or updates to stored graphics processor contexts.

公开(公告)号：US20230101997A1

公开(公告)日：2023-03-30

申请号：US17490290

申请日：2021-09-30

Applicant: Intel Corporation

Inventor： Nikos Kaburlasos ,  Rodrigo De Oliveira Vivi ,  Phani Kumar Kandula ,  Marc Beuchat ,  Mark J. Luckeroth ,  Eric J.M. Moret ,  David N. Lombard ,  John Kelbert ,  Brad Bittel

IPC: G06F1/3296 ,  G06F1/3228 ,  G06F1/08

Abstract: Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.

公开(公告)号：US11409341B2

公开(公告)日：2022-08-09

申请号：US16590197

申请日：2019-10-01

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Ankur Shah ,  Marc Beuchat

IPC: G06F1/00 ,  G06F1/20 ,  G06T1/60 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210096620A1

公开(公告)日：2021-04-01

申请号：US16590197

申请日：2019-10-01

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Ankur Shah ,  Marc Beuchat

IPC: G06F1/20 ,  G06T1/20 ,  G06T1/60

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US10528114B2

公开(公告)日：2020-01-07

申请号：US15148115

申请日：2016-05-06

Applicant: Intel Corporation

Inventor： Marc Beuchat ,  Jason Tanner

IPC: G06F1/32 ,  G06T1/20 ,  G06F1/324 ,  G06F1/3228

Abstract: One embodiment provides an apparatus. The apparatus includes a graphics processor and power management logic. The graphics processor includes display engine logic and encoder logic. The power management logic is to adjust an operating frequency of the encoder logic based, at least in part, on an encode time duration and based, at least in part, on a frame period.

公开(公告)号：US20190215769A1

公开(公告)日：2019-07-11

申请号：US16243029

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Eric C. Samson ,  Murali Ramadoss ,  Marc Beuchat

IPC: H04W52/02 ,  G06T1/20 ,  H04W52/18

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.