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    HIGH-PERFORMANCE INPUT-OUTPUT DEVICES SUPPORTING SCALABLE VIRTUALIZATION
    12.
    发明申请
    HIGH-PERFORMANCE INPUT-OUTPUT DEVICES SUPPORTING SCALABLE VIRTUALIZATION 有权

    公开(公告)号：US20250117264A1

    公开(公告)日：2025-04-10

    申请号：US18935248

    申请日：2024-11-01

    Applicant: Intel Corporation

    Inventor： Utkarsh Y. KAKAIYA ,  Rajesh M. SANKARAN ,  Sanjay KUMAR ,  Kun TIAN ,  Philip LANTZ

    IPC: G06F9/54 ,  G06F9/455 ,  G06F9/48 ,  G06F15/17

    Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

    LIVE-MIGRATION OF PINNED DIRECT MEMORY ACCESS PAGES TO SUPPORT MEMORY HOT-REMOVE
    13.
    发明申请
    LIVE-MIGRATION OF PINNED DIRECT MEMORY ACCESS PAGES TO SUPPORT MEMORY HOT-REMOVE 有权

    公开(公告)号：US20220374354A1

    公开(公告)日：2022-11-24

    申请号：US17844568

    申请日：2022-06-20

    Applicant: Intel Corporation

    Inventor： Sridhar MUTHRASANALLUR ,  Rajesh M. SANKARAN

    IPC: G06F12/02

    Abstract: A system on chip (SoC) coupled to a memory can perform a hot-remove operation in a computer system. In a hot-remove operation, software (e.g., operating system) and hardware (e.g., memory controller and interconnect circuitry) components migrate memory content from one region to another target region in the memory. A peripheral device can have direct memory access (DMA) to a page in the region of memory that is being hot-removed. The interconnect circuitry can migrate the page to the target region while maintaining the peripheral device's direct access to the memory. Interconnect circuitry uses hardware mirroring in response to a write command to a memory address in the region being hot-removed. With hardware mirroring, the data is stored in two locations; the first location is the memory address in the region being moved, and the second location is a memory address in the target region.

    PAGE FAULT MANAGEMENT TECHNOLOGIES
    14.
    发明申请
    PAGE FAULT MANAGEMENT TECHNOLOGIES 有权

    公开(公告)号：US20220197805A1

    公开(公告)日：2022-06-23

    申请号：US17479954

    申请日：2021-09-20

    Applicant: Intel Corporation

    Inventor： Shaopeng HE ,  Anjali Singhai JAIN ,  Patrick MALONEY ,  Yadong LI ,  Chih-Jen CHANG ,  Kun TIAN ,  Yan ZHAO ,  Rajesh M. SANKARAN ,  Ashok RAJ

    IPC: G06F12/0831 ,  G06F12/1009 ,  G06F9/455

    Abstract: Examples described herein relate to at least one processor and circuitry, when operational, to: in connection with a request from a device to copy data to a destination memory address: based on a page fault, copy the data to a backup page and after determination of a virtual-to-physical address translation, copy the data from the backup page to a destination page identified by the physical address. In some examples, the copy the data to a backup page is based on a page fault and an indication that a target buffer for the data is at or above a threshold level of fullness. In some examples, copying the data to a backup page includes: receive the physical address of the backup page from the device and copy data from the device to the backup page based on identification of the backup page.

    SCALABLE INTERRUPT VIRTUALIZATION FOR INPUT/OUTPUT DEVICES
    15.
    发明申请
    SCALABLE INTERRUPT VIRTUALIZATION FOR INPUT/OUTPUT DEVICES 有权

    公开(公告)号：US20220107910A1

    公开(公告)日：2022-04-07

    申请号：US17550977

    申请日：2021-12-14

    Applicant: Intel Corporation

    Inventor： Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Philip R. LANTZ ,  Utkarsh Y. KAKAIYA ,  Kun TIAN

    IPC: G06F13/24 ,  G06F9/455 ,  G06F9/48

    Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.

    NETWORK INTERFACE FOR DATA TRANSPORT IN HETEROGENEOUS COMPUTING ENVIRONMENTS
    18.
    发明申请
    NETWORK INTERFACE FOR DATA TRANSPORT IN HETEROGENEOUS COMPUTING ENVIRONMENTS 有权

    公开(公告)号：US20210112003A1

    公开(公告)日：2021-04-15

    申请号：US17129756

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

    IPC: H04L12/747 ,  G06F13/28 ,  H04L12/861 ,  G06F12/1081 ,  H04L12/773

    Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

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