公开(公告)号：US20190227981A1

公开(公告)日：2019-07-25

申请号：US16368983

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram ,  Jawad B. Khan

IPC: G06F15/78 ,  G06F17/16 ,  G06F15/80

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

公开(公告)号：US10331360B2

公开(公告)日：2019-06-25

申请号：US15281006

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Albert Fazio ,  Derchang Kau ,  Shekoufeh Qawami

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G11C13/00

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

公开(公告)号：US09818458B1

公开(公告)日：2017-11-14

申请号：US14862269

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Sowmiya Jayachandran ,  Rajesh Sundaram ,  Robert Faber

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/02 ,  G11C5/147 ,  G11C5/148 ,  G11C7/00 ,  Y02D10/14

Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

公开(公告)号：US11237903B2

公开(公告)日：2022-02-01

申请号：US16451545

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Wei Wu ,  Chetan Chauhan ,  Srikanth Srinivasan ,  Shigeki Tomishima

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

Abstract: Technologies for provisioning error-corrected data for use in in-memory compute operations include a memory that includes a memory media having multiple memory partitions and media access circuitry coupled to the memory media. The media access circuitry is to receive a request to perform an in-memory compute operation on data from the memory media. The request specifies a memory partition of the memory media in which the data is located. The media access circuitry reads the data from the memory partition. The media access circuitry performs error correction on the read data to produce error-corrected read data and stores the error-corrected read data in a temporary buffer for access by one or more in-memory compute operations, in addition to the requested in-memory compute operation.

公开(公告)号：US11204718B2

公开(公告)日：2021-12-21

申请号：US16586428

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Zion S. Kwok ,  Muthukumar Swaminathan

IPC: G06F3/06

Abstract: Embodiments are directed towards apparatuses, methods, and systems including a pre-read command to eliminate an additional access of read data from a storage location of a memory device. In embodiments, a memory controller issues a pre-read command to store read data in a pre-read latch. In embodiments, the command is issued during a first access of the read data from a storage location in connection with a modify-write operation of the read data. In embodiments, the pre-read latch is located in or coupled to a selected partition of a memory device that includes the storage location that stores the read data. In embodiments, the memory controller subsequently issues a modify-write command to compare the read data stored in the pre-read latch with incoming data, to eliminate a need for a second access of the storage location during completion of the modify-write operation. Additional embodiments may be described and claimed.

公开(公告)号：US11182158B2

公开(公告)日：2021-11-23

申请号：US16419483

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram

IPC: G06F12/00 ,  G06F9/30 ,  G06F9/50

Abstract: Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

公开(公告)号：US11080226B2

公开(公告)日：2021-08-03

申请号：US16737779

申请日：2020-01-08

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram ,  Jawad B. Khan

IPC: G06F15/78 ,  G06F17/16 ,  G06N3/00 ,  G06F15/80

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

公开(公告)号：US11010061B2

公开(公告)日：2021-05-18

申请号：US16428802

申请日：2019-05-31

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Albert Fazio ,  Derchang Kau ,  Shekoufeh Qawami

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G11C13/00

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

公开(公告)号：US20200301825A1

公开(公告)日：2020-09-24

申请号：US15930889

申请日：2020-05-13

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Sourabh Dongaonkar ,  Rajesh Sundaram ,  Jawad Khan ,  Sandeep Guliani ,  Dipanjan Sengupta ,  Mariano Tepper

IPC: G06F12/02 ,  G06F16/27

Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.

公开(公告)号：US20190228809A1

公开(公告)日：2019-07-25

申请号：US16370011

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Srikanth Srinivasan ,  Rajesh Sundaram ,  Jawad B. Khan ,  Shigeki Tomishima ,  Sriram Vangal ,  Chetan Chauhan

IPC: G11C7/10 ,  G06F17/16 ,  G06N3/08 ,  G06F9/54 ,  G06F3/06

Abstract: Technologies for providing high efficiency compute architecture on cross point memory for artificial intelligence operations include a memory that includes media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is to access matrix data from the memory media, including broadcasting matrix data associated with one partition of the memory media to multiple other partitions of the memory media. The media access circuitry is also to perform, with each of multiple compute logic units associated with different partitions of the memory media, a tensor operation on the matrix data and write, to the memory media, resultant data indicative of a result of the tensor operation.