公开(公告)号：US20170288869A1

公开(公告)日：2017-10-05

申请号：US15628386

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Jiangtao Li ,  Anand Rajan ,  Roel Maes ,  Sanu K. Mathew ,  Ram Krishnamurthy ,  Ernie Brickell

IPC: H04L9/08

CPC classification number: H04L9/0891 ,  G09C1/00 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/0866 ,  H04L9/0894 ,  H04L2209/12

Abstract: Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processor/apparatus. In one embodiment, the apparatus includes a physically unclonable functions (PUF) circuit to generate a hardware key based on at least one manufacturing variation of the apparatus and a nonvolatile memory coupled to the PUF circuit, the nonvolatile memory to store an encrypted key, the encrypted key comprising a first key encrypted using the hardware key. The apparatus further includes a hardware cipher component coupled to the nonvolatile memory and the PUF circuit, the hardware cipher component to decrypt the encrypted key stored in the nonvolatile memory with at least the hardware key to generate a decrypted copy of the first key and fixed logic circuitry coupled to the PUF circuit and the hardware cipher component, the fixed logic circuitry to verify that the decrypted copy of the first key is valid.

公开(公告)号：US09641160B2

公开(公告)日：2017-05-02

申请号：US14635849

申请日：2015-03-02

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven Hsu ,  Ram Krishnamurthy

IPC: H03K3/356 ,  H03K3/3562 ,  H03K3/012 ,  H03K3/037

CPC classification number: H03K3/356008 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/35625

Abstract: Embodiments include apparatuses, methods, and systems for state retention electronic devices. In embodiments, an electronic device may include a state retention flip-flop having a plurality of P-type metal oxide semiconductor (PMOS) devices coupled with a common N-well, with one or more of the plurality of PMOS devices powered by an always-on supply and one or more of the plurality of PMOS devices powered by a power-gated supply. Other embodiments may be described and claimed.

公开(公告)号：US20240356552A1

公开(公告)日：2024-10-24

申请号：US18305147

申请日：2023-04-21

Applicant: Intel Corporation

Inventor： Steven Hsu ,  Amit Agarwal ,  Ram Krishnamurthy

IPC: H03K19/0185 ,  G06F3/06 ,  G11C11/418 ,  G11C11/419 ,  H03K19/21

CPC classification number: H03K19/018521 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C11/418 ,  G11C11/419 ,  H03K19/21

Abstract: A disclosed example includes a read local bitline; and a plurality of pulldown transistor circuits coupled to the read local bitline, a first one of the pulldown transistor circuits including: a first low threshold voltage transistor, the first low threshold voltage transistor including a first drain terminal coupled to the read local bitline; and a second low threshold voltage transistor, the second low threshold voltage transistor including a second drain terminal coupled to a first source terminal of the first low threshold voltage transistor, the second low threshold voltage transistor to persist a voltage level detectable at a gate terminal of the second low threshold voltage transistor, the voltage level representative of a bit of information.

公开(公告)号：US20240242067A1

公开(公告)日：2024-07-18

申请号：US18621802

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Songtao Liu ,  Haisheng Rong ,  Mozhgan Mansuri ,  Ram Krishnamurthy

IPC: G06N3/067

CPC classification number: G06N3/067

Abstract: Systems, apparatuses and methods include technology that executes, with a first plurality of panels, a first matrix-matrix multiplication operation of a first layer of an optical neural network (ONN) to generate output optical signals based on input optical signals that pass through an optical path of the ONN, and weights of the first layer of the ONN. The first plurality of panels includes an input panel, a weight panel and a photodetector panel. The executing includes generating, with the input panel, the input optical signals, where the input optical signals represent an input to the first matrix-matrix multiplication operation of the first layer of the ONN, representing, with the weight panel, the weights of the first layer of the ONN, and generating, with the photodetector panel, output photodetector signals based on the output optical signals that are generated based on the input optical signals and the weights.

公开(公告)号：US11663452B2

公开(公告)日：2023-05-30

申请号：US16583217

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Ram Krishnamurthy ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Deepak Vinayak Kadetotad

IPC: G06F17/16 ,  G06N3/063 ,  G06F7/544 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06F17/16 ,  G06N3/04

Abstract: An apparatus is described. The apparatus includes a circuit to process a binary neural network. The circuit includes an array of processing cores, wherein, processing cores of the array of processing cores are to process different respective areas of a weight matrix of the binary neural network. The processing cores each include add circuitry to add only those weights of an i layer of the binary neural network that are to be effectively multiplied by a non zero nodal output of an i−1 layer of the binary neural network.

公开(公告)号：US11442103B2

公开(公告)日：2022-09-13

申请号：US17240877

申请日：2021-04-26

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Ram Krishnamurthy ,  Satish Damaraju ,  Steven Hsu ,  Simeon Realov

IPC: G01R31/317 ,  G01R31/3177 ,  H03K3/037 ,  G01R31/3185

Abstract: An apparatus is provided which comprises: a multi-bit quad latch with an internally coupled level sensitive scan circuitry; and a combinational logic coupled to an output of the multi-bit quad latch. Another apparatus is provided which comprises: a plurality of sequential logic circuitries; and a clocking circuitry comprising inverters, wherein the clocking circuitry is shared by the plurality of sequential logic circuitries.

公开(公告)号：US20220224316A1

公开(公告)日：2022-07-14

申请号：US17711638

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

IPC: H03K3/037 ,  G01R31/3177 ,  H03K3/038 ,  H03K19/20

Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

公开(公告)号：US11138499B2

公开(公告)日：2021-10-05

申请号：US16147176

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Jack T. Kavalieros ,  Ian A. Young ,  Sasikanth Manipatruni ,  Ram Krishnamurthy ,  Uygar Avci ,  Gregory K. Chen ,  Amrita Mathuriya ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Nazila Haratipour ,  Van H. Le

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10 ,  G11C11/419 ,  G11C11/409 ,  G11C11/22

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US11061646B2

公开(公告)日：2021-07-13

申请号：US16147004

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Phil Knag ,  Gregory K. Chen ,  Raghavan Kumar ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G06F7/544 ,  G11C8/10 ,  G11C8/08 ,  G11C7/12 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/56 ,  G11C11/4091 ,  G06G7/16 ,  G11C11/419

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

公开(公告)号：US20200242459A1

公开(公告)日：2020-07-30

申请号：US16262583

申请日：2019-01-30

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ram Krishnamurthy ,  Amrita Mathuriya ,  Dmitri Nikonov ,  Ian Young

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06F17/16

Abstract: Techniques are provided for implementing a hybrid processing architecture comprising a general-purpose processor (CPU) and a neural processing unit (NPU), coupled to an analog in-memory artificial intelligence (AI) processor. According to an embodiment, the hybrid processor implements an AI instruction set including instructions to perform analog in-memory computations. The AI processor comprises one or more layers, the NN layers including memory circuitry and analog processing circuitry. The memory circuitry is configured to store the weighting factors and the input data. The analog processing circuitry is configured to perform analog calculations on the stored weighting factors and the stored input data in accordance with the execution, by the NPU, of instruction from the AI instruction set. The AI instruction set includes instructions to perform dot products, multiplication, differencing, normalization, pooling, thresholding, transposition, and backpropagation training. The NN layers are configured as convolutional NN layers and/or fully connected NN layers.