公开(公告)号：US20160204246A1

公开(公告)日：2016-07-14

申请号：US14914102

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

Abstract translation: 描述了具有最大化顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍片具有沿着半导体鳍片的长度与一对突出外部部分间隔开的中心突出或凹陷部分。 在半导体翅片的中央突出或凹陷部分上设置包覆层区域。 栅极堆叠设置在包覆层区域上。 源极/漏极区域设置在半导体鳍片的一对突出的外部段中。

公开(公告)号：US20160190319A1

公开(公告)日：2016-06-30

申请号：US14912059

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： JACK T. KAVALIEROS ,  MARKO RADOSAVLJEVIC ,  MATTHEW V. METZ ,  HAN WUI THEN ,  BENJAMIN CHU-KUNG ,  VAN H. LE ,  NILOY MUKHERJEE ,  SANSAPTAK DASGUPTA ,  RAVI PILLARISETTY ,  GILBERT DEWEY ,  ROBERT S. CHAU ,  NANCY M. ZELICK ,  WILLY RACHMADY

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/267 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Non-planar semiconductor devices having multi-layered compliant substrates and methods of fabricating such non-planar semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a lower portion composed of a first semiconductor material with a first lattice constant (L1), and has an upper portion composed of a second semiconductor material with a second lattice constant (L2). A cladding layer is disposed on the upper portion, but not on the lower portion, of the semiconductor fin. The cladding layer is composed of a third semiconductor material with a third lattice constant (L3), wherein L3>L2>L1. A gate stack is disposed on a channel region of the cladding layer. Source/drain regions are disposed on either side of the channel region.

Abstract translation: 描述了具有多层柔性衬底的非平面半导体器件以及制造这种非平面半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍具有由具有第一晶格常数（L1）的第一半导体材料构成的下部，并且具有由具有第二晶格常数（L2）的第二半导体材料构成的上部。 在半导体翅片的上部而不是下部设置包覆层。 包覆层由具有第三晶格常数（L3）的第三半导体材料构成，其中L3> L2> L1。 栅堆叠设置在包层的沟道区上。 源极/漏极区域设置在沟道区域的两侧。

公开(公告)号：US20190279908A1

公开(公告)日：2019-09-12

申请号：US16302414

申请日：2016-06-22

Applicant: INTEL CORPORATION

Inventor： MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  PETER G. TOLCHINSKY

IPC: H01L21/8258 ,  H01L29/04 ,  H01L29/20 ,  H01L29/16 ,  H01L29/08 ,  H01L21/02 ,  H01L27/12

Abstract: Techniques are disclosed for monolithic co-integration of silicon (Si)-based transistor devices and III-N semiconductor-based transistor devices over a commonly shared semiconductor substrate. In accordance with some embodiments, the disclosed techniques may be used to provide a silicon-on-insulator (SOI) or other semiconductor-on-insulator structure including: (1) a Si (111) surface available for formation of III-N-based n-channel devices; and (2) a Si (100) surface available for formation of Si-based p-channel devices, n-channel devices, or both. Further processing may be performed, in accordance with some embodiments, to provide n-channel and p-channel devices over the Si (111) and Si (100) surfaces, as desired. In accordance with some embodiments, the disclosed techniques may be used to provide co-integrated III-N-based n-type metal-oxide-semiconductor (NMOS) devices and Si-based p-type metal-oxide-semiconductor (PMOS), NMOS, or complementary MOS (CMOS) devices with different step heights or with a given degree of co-planarity, as desired for a given target application or end-use.

公开(公告)号：US20190221660A1

公开(公告)日：2019-07-18

申请号：US16306292

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  HAN WUI THEN ,  MARKO RADOSAVLJEVIC ,  SANAZ K. GARDNER ,  SEUNG HOON SUNG

IPC: H01L29/778 ,  H01L29/51 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7786

Abstract: A gate stack structure is disclosed for inhibiting charge leakage in III-V transistor devices. The techniques are particularly well-suited for use in enhancement-mode MOSHEMTs, but can also be used in other transistor designs susceptible to charge spillover and unintended channel formation in the gate stack. In an example embodiment, the techniques are realized in a transistor having a III-N gate stack over a gallium nitride (GaN) channel layer. The gate stack is configured with a relatively thick barrier structure and wide bandgap III-N materials to prevent or otherwise reduce channel charge spillover resulting from tunneling or thermionic processes at high gate voltages. The barrier structure is configured to manage lattice mismatch conditions, so as to provide a robust high performance transistor design. In some cases, the gate stack is used in conjunction with an access region polarization layer to induce two-dimensional electron gas (2DEG) in the channel layer.

公开(公告)号：US20190214464A1

公开(公告)日：2019-07-11

申请号：US15772742

申请日：2015-12-14

Applicant: INTEL CORPORATION

Inventor： MARKO RADOSAVLJEVIC ,  HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  SANAZ GARDNER ,  SEUNG HOON SUNG

IPC: H01L29/10 ,  H01L29/778 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/10 ,  H01L21/30612 ,  H01L21/3086 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7786

Abstract: Techniques are disclosed for producing integrated circuit structures that include one or more geometrically manipulated polarization layers. The disclosed structures can be formed, for instance, using spacer erosion methods in which more than one type of spacer material is deposited on a polarization layer, and the spacer materials and underlying regions of the polarization layer may then be selectively etched in sequence to provide a desired profile shape to the polarization layer. Geometrically manipulated polarization layers as disclosed herein may be formed to be thinner in regions closer to the gate than in other regions, in some embodiments. The disclosed structures may eliminate the need for a field plate and may also be configured with polarization layers that are shorter in lateral length than polarization layers of uniform thickness without sacrificing performance capability. Additionally, the disclosed techniques may provide increased voltage breakdown without sacrificing Ron.

公开(公告)号：US20180331222A1

公开(公告)日：2018-11-15

申请号：US15774449

申请日：2015-12-09

Applicant: INTEL CORPORATION

Inventor： SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  HAN WUI THEN

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66 ,  H01L29/24

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66522

Abstract: Techniques are disclosed for increasing the performance of III-N p-channel devices, such as GaN p-channel transistors. Increased performance is obtained by applying compressive strain to the GaN p-channel. Compressive strain is applied to the GaN p-channel by epitaxially growing a source/drain material on or in the GaN. The source/drain material has a larger lattice constant than does the GaN and puts the p-channel under compressive strain. Numerous III-N material systems can be used

公开(公告)号：US20180331182A1

公开(公告)日：2018-11-15

申请号：US15774064

申请日：2015-12-07

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  SANAZ K. GARDNER ,  SEUNG HOON SUNG

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/267

CPC classification number: H01L29/0847 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/785

Abstract: Techniques are disclosed for forming self-aligned transistor structures including two-dimensional electron gas (2DEG) source/drain tip portions or tips. In some cases, the 2DEG source/drain tips utilize polarization doping to enable ultra-short transistor channel lengths of less than 20 nm, for example, and create highly conductive, thin source/drain tip portions in transistor devices. In some instances, the 2DEG source/drain tips can be formed by self-aligned regrowth of a polarization layer over a base III-V compound layer and on either side of a dummy gate, in locations to be substantially covered by spacers. In some cases, the III-V base layer may include gallium nitride (GaN) or indium gallium nitride (InGaN), for example, and the polarization layer may include aluminum indium nitride (AlInN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN), for example.

公开(公告)号：US20180331082A1

公开(公告)日：2018-11-15

申请号：US15777500

申请日：2015-12-21

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  SEUNG HOON SUNG ,  SANAZ GARDNER

IPC: H01L25/16 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/08 ,  H01L29/778 ,  H01L29/20 ,  H01L29/423

Abstract: Techniques are disclosed for forming monolithic integrated circuit semiconductor structures that include a III-V portion implemented with III-N semiconductor materials, such as gallium nitride, indium nitride, aluminum nitride, and mixtures thereof. The disclosed semiconductor structures may further include a CMOS portion implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). The disclosed techniques can be used to form highly-efficient envelope tracking devices that include a voltage regulator and a radio frequency (RF) power amplifier that may both be located on the III-N portion of the semiconductor structure. Either of the CMOS or III-N portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of a III-N voltage regulator and RF power amplifier along with column IV CMOS devices on a single substrate.

公开(公告)号：US20180308965A1

公开(公告)日：2018-10-25

申请号：US15771752

申请日：2015-12-02

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L27/092 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L21/8258

CPC classification number: H01L29/7781 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/7786

Abstract: Techniques are disclosed for co-integrating transition metal dichalcogenide (TMDC)-based p-channel transistor devices and III-N semiconductor-based n-channel transistor devices. In accordance with some embodiments, a p-channel transistor device configured as described herein may include a layer of TMDC material such as, for example, tungsten diselenide, tungsten disulfide, molybdenum diselenide, or molybdenum disulfide, and an n-channel transistor device configured as described herein may include a layer of III-V material such as, for example, gallium nitride, aluminum nitride, aluminum gallium nitride, and indium aluminum nitride. Transistor structures provided as described herein may be utilized, for instance, in power delivery applications where III-N semiconductor-based n-channel power transistor devices can benefit from being integrated with low-leakage, high-performance p-channel devices providing logic and control circuitry. In some cases, a TMDC-based transistor provided as described herein may exhibit p-channel mobility in excess of bulk Si and thus may exhibit faster performance than traditional Si-based p-channel transistors.

公开(公告)号：US20160204207A1

公开(公告)日：2016-07-14

申请号：US14913173

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： HAN WUI THEN ,  SANSAPTAK DASGUPTA ,  MARKO RADOSAVLJEVIC ,  ROBERT S. CHAU ,  SEUNG HOON SUNG ,  SANAZ K. GARDNER

IPC: H01L29/20 ,  H01L29/207 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0254 ,  H01L21/28264 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: Enhancement mode gallium nitride (GaN) semiconductor devices having a composite high-k metal gate stack and methods of fabricating such devices are described. In an example, a semiconductor device includes a gallium nitride (GaN) channel region disposed above a substrate. A gate stack is disposed on the GaN channel region. The gate stack includes a composite gate dielectric layer disposed directly between the GaN channel region and a gate electrode. The composite gate dielectric layer includes a high band gap Group III-N layer, a first high-K dielectric oxide layer, and a second high-K dielectric oxide layer having a higher dielectric constant than the first high-K dielectric oxide layer. Source/drain regions are disposed on either side of the GaN channel region.

Abstract translation: 描述了具有复合高k金属栅叠层的增强模式氮化镓（GaN）半导体器件及其制造方法。 在一个示例中，半导体器件包括设置在衬底上方的氮化镓（GaN）沟道区。 栅叠层设置在GaN沟道区上。 栅极堆叠包括直接设置在GaN沟道区和栅电极之间的复合栅介质层。 复合栅极电介质层包括具有比第一高K电介质氧化物层更高的介电常数的高带隙组III-N层，第一高K电介质氧化物层和第二高K电介质氧化物层。 源/漏区设置在GaN沟道区的两侧。