公开(公告)号：US20150074373A1

公开(公告)日：2015-03-12

申请号：US13977727

申请日：2012-06-02

Applicant: INTEL CORPORATION

Inventor： Zeev Sperber ,  Robert Valentine ,  Shlomo Raikin ,  Stanislav Shwartsman ,  Gal Ofir ,  Igor Yanover ,  Guy Patkin ,  Levy Ofer

IPC: G06F15/78 ,  G06F9/30

CPC classification number: G06F15/7839 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3808 ,  G06F9/383

Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

Abstract translation: 公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。 设备的实施例可以包括：解码逻辑以解码散射/收集指令并产生微操作。 索引数组保存一组索引和一组对应的掩码元素。 有限状态机有助于散射操作。 地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。 正在生成的每组地址的缓冲区中分配存储空间。 与生成的地址集相对应的数据元素被复制到缓冲器。 如果对应的掩码元素具有所述第一值并且掩模元素被响应于它们各自的存储的完成而被改变为第二值，则访问该集合的地址以存储数据元素。

公开(公告)号：US20230088947A1

公开(公告)日：2023-03-23

申请号：US17993591

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC: G06F11/14 ,  G06F11/10

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US20210318932A1

公开(公告)日：2021-10-14

申请号：US17356157

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC: G06F11/14 ,  G06F11/10

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US09183161B2

公开(公告)日：2015-11-10

申请号：US13730563

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Gur Hildesheim ,  Ittai Anati ,  Hisham Shafi ,  Shlomo Raikin ,  Gideon Gerzon ,  Uday R Savagaonkar ,  Carlos V Rozas ,  Francis X McKeen ,  Michael A Goldsmith ,  Dewan Prashant

IPC: G06F12/14 ,  G06F21/53 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/145 ,  G06F12/084 ,  G06F12/1027 ,  G06F12/1483 ,  G06F21/53

Abstract: An apparatus and method for managing a protection table by a processor. For example, a processor according to one embodiment of the invention comprises: protection table management logic to manage a protection table, the protection table having an entry for each protected page or each group of protected pages in memory; wherein the protection table management logic prevents direct access to the protection table by user application program code and operating system program code but permits direct access by the processor.

Abstract translation: 一种用于由处理器管理保护表的装置和方法。 例如，根据本发明的一个实施例的处理器包括：保护表管理逻辑以管理保护表，所述保护表具有用于每个受保护页面的条目或存储器中每组受保护页面; 其中保护表管理逻辑防止用户应用程序代码和操作系统程序代码直接访问保护表，但允许处理器直接访问。

公开(公告)号：US10152451B2

公开(公告)日：2018-12-11

申请号：US15490743

申请日：2017-04-18

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Robert Valentine ,  Shlomo Raikin ,  Stanislav Shwartsman ,  Gal Ofir ,  Igor Yanover ,  Guy Patkin ,  Ofer Levy

IPC: G06F9/00 ,  G06F15/78 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

公开(公告)号：US10146737B2

公开(公告)日：2018-12-04

申请号：US14616323

申请日：2015-02-06

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC: G06F9/00 ,  G06F15/80 ,  G06F9/30 ,  G06F9/38

Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

公开(公告)号：US09971705B2

公开(公告)日：2018-05-15

申请号：US15048400

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Gur Hildesheim ,  Shlomo Raikin ,  Ittai Anati ,  Gideon Gerzon ,  Uday Savagaonkar ,  Francis Mckeen ,  Carlos Rozas ,  Michael Goldsmith ,  Prashant Dewan

IPC: G06F12/10 ,  G06F12/109 ,  G06F12/1036 ,  G06F12/02

CPC classification number: G06F12/109 ,  G06F12/0284 ,  G06F12/1036 ,  G06F2212/656 ,  G06F2212/657

Abstract: Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.

公开(公告)号：US09734079B2

公开(公告)日：2017-08-15

申请号：US13931701

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Dannie G. Feekes ,  Shlomo Raikin ,  Blaise Fanning ,  Joydeep Ray ,  Julius Mandelblat ,  Ariel Berkovits ,  Eran Shifer ,  Zvika Greenfield ,  Evgeny Bolotin

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/06 ,  G06F1/32

CPC classification number: G06F12/0893 ,  G06F1/32 ,  G06F1/3275 ,  G06F12/063 ,  G06F12/08 ,  G06F12/0866 ,  G06F2212/205 ,  G06F2212/206 ,  G06F2212/281 ,  G06F2212/604 ,  G06F2212/608 ,  Y02D10/13 ,  Y02D10/14

Abstract: Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

公开(公告)号：US09424198B2

公开(公告)日：2016-08-23

申请号：US13691107

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Shlomo Raikin ,  Zvika Greenfield

IPC: G06F12/08 ,  G06F12/06

CPC classification number: G06F12/0893 ,  G06F12/0646 ,  G06F12/0864 ,  G06F12/0888 ,  G06F2212/15

Abstract: A processor includes at least one execution unit, a near memory, and memory management logic to manage the near memory and a far memory external to the processor as a unified exclusive memory. Each of a plurality of data blocks may be exclusively stored in either the far memory or the near memory. The unified exclusive memory space may be divided into a plurality of sets and a plurality of ways. In response to a request for a first block stored in the far memory, the memory management logic may move the first block from the far memory to the near memory, and may move a second block from the near memory to the far memory. A tag buffer may store tags associated with blocks being moved between the near memory and the far memory. Fill and drain buffers may also be used. Other implementations are described and claimed.

Abstract translation: 处理器包括至少一个执行单元，近存储器和存储器管理逻辑，用于将近端存储器和作为统一独占存储器的处理器外部的远处存储器进行管理。 多个数据块中的每一个可以专门存储在远存储器或近存储器中。 统一的独占存储器空间可以被分成多个集合和多个方式。 响应于对存储在远存储器中的第一块的请求，存储器管理逻辑可以将第一块从远存储器移动到近存储器，并且可以将第二块从近存储器移动到远存储器。 标签缓冲器可以存储与在近存储器和远存储器之间移动的块相关联的标签。 也可以使用填充和排出缓冲液。 描述和要求保护其他实现。