公开(公告)号：US20250107209A1

公开(公告)日：2025-03-27

申请号：US18473618

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Yoon Jung Chang ,  Zafrullah Jagoo ,  Sridhar Govindaraju

IPC: H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Techniques are provided to form an integrated circuit having a gate electrode that includes at least one layer containing molybdenum. A transistor includes a gate structure having a gate electrode on a gate dielectric. The gate structure extends around a fin or any number of nanowires (or nanoribbons or nanosheets) of semiconductor material. The gate electrode includes one or more conductive layers on the gate dielectric with at least one of those conductive layers containing molybdenum (e.g., molybdenum nitride). The conductive layer having molybdenum may be used during the formation of the gate dielectric (e.g., during an annealing process), thus resulting in a higher quality gate dielectric.

公开(公告)号：US11756833B2

公开(公告)日：2023-09-12

申请号：US17738968

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/535 ,  H01L23/5329 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/42372 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/0002

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US11380592B2

公开(公告)日：2022-07-05

申请号：US17069265

申请日：2020-10-13

Applicant: INTEL CORPORATION

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/12

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US11217582B2

公开(公告)日：2022-01-04

申请号：US15941647

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon ,  Sairam Subramanian

IPC: H01L27/088 ,  H01L29/66 ,  H01L23/528 ,  H01L29/06 ,  H01L21/8234

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US20200066841A1

公开(公告)日：2020-02-27

申请号：US16461071

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Ashutosh Sagar ,  Sridhar Govindaraju

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66

Abstract: An apparatus includes a non-planar semiconductor body; and a contact for the semiconductor body. The contact includes an epitaxial material that is formed on and contacts the semiconductor body. The contact includes a second material that is formed on and contacts the epitaxial material; and the second material at least partially conforms to an undercut of the epitaxial material.

公开(公告)号：US10468305B2

公开(公告)日：2019-11-05

申请号：US15415495

申请日：2017-01-25

Applicant: INTEL CORPORATION

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L23/00 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L21/84

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US09761497B2

公开(公告)日：2017-09-12

申请号：US15008325

申请日：2016-01-27

Applicant: INTEL CORPORATION

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20170133276A1

公开(公告)日：2017-05-11

申请号：US15415495

申请日：2017-01-25

Applicant: INTEL CORPORATION

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L23/532 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L23/535 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16225 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.