公开(公告)号：US20240213100A1

公开(公告)日：2024-06-27

申请号：US18087879

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Yulia Gotlib ,  Chiao-ti Huang ,  Bishwajit Debnath ,  Anupama Bowonder ,  Matthew J. Prince

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823878 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L24/16 ,  H01L2224/16225

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a hybrid material structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that includes a hybrid structure having both a low-k dielectric material and a high-k dielectric material. The gate cut includes an outer layer having a high-k dielectric material and a dielectric fill on the dielectric layer having a low-k dielectric material. The inclusion of low-k dielectric material reduces the parasitic capacitance between adjacent conductive layers around or within the gate cut.

公开(公告)号：US20250113600A1

公开(公告)日：2025-04-03

申请号：US18477947

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Yulia Gotlib ,  Matthew J. Prince ,  Sachin S. Vaidya ,  Ying Zhou ,  Xiaoye Qin ,  Ryan Pearce ,  Andrew Arnold ,  Chiao-Ti Huang

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having an improved liner structure to prevent oxidation of the gate electrode. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. In an example, the gate cut includes a silicon nitride dielectric liner with a higher percentage of Si—H bonds compared to Si—N bonds at an interface between the dielectric liner and the gate structure. The liner may also include a higher percentage of Si—N bonds compared to Si—H bonds at an interface between the dielectric liner and a dielectric fill on the dielectric liner.

公开(公告)号：US12094780B2

公开(公告)日：2024-09-17

申请号：US18223981

申请日：2023-07-19

Applicant: Intel Corporation

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  G06F30/39 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  G06F30/39 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00 ,  H01L2924/0002

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20240194732A1

公开(公告)日：2024-06-13

申请号：US18077658

申请日：2022-12-08

Applicant: Intel Corporation

Inventor： Matthew J. Prince ,  Amitesh Shrivastava ,  Walid M. Hafez ,  Anurag A. Jain ,  Gary Ding ,  Sharath Hegde ,  Caitlin M. Kilroy ,  Inki Kim

IPC: H01L29/06 ,  H01L21/033 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/0332 ,  H01L21/0337 ,  H01L29/0843 ,  H01L29/66439

Abstract: Techniques are provided herein to use a chemical mechanical polishing (CMP) process to polish carbon hard mask (CHM) for a variety of useful semiconductor fabrication applications. In one example, a CMP process that uses a silica-based slurry is used to polish CHM formed over gate trenches of different widths, such that the CHM can recess to substantially the same height within the gate trenches of different widths. In another example, CHM may be deposited over groups of fins or a backbone structure and polished using a CMP process with a silica-based slurry to ensure a planar top surface of CHM over the groups of fins or backbone structure.

公开(公告)号：US20240105800A1

公开(公告)日：2024-03-28

申请号：US17951532

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Reza Bayati ,  Alison V. Davis ,  Ramy Ghostine ,  Matthew J. Prince

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0673 ,  H01L29/78696

Abstract: Techniques are described to form semiconductor devices that include one or more gate cuts having a very high aspect ratio (e.g., an aspect ratio of 5:1 or greater). A semiconductor device includes a conductive material that is part of a transistor gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure. A plasma etching process may be performed to form the gate cut with a very high height-to-width aspect ratio with little to no tapering in its sidewall profile, so as to enable densely integrated devices. Furthermore, an etching process may be performed on a gate masking structure used to pattern the location of the gate cuts to ensure that the gate masking structure has low sidewall taper and sufficiently opened enough to expose the underlying gate.

公开(公告)号：US20160141212A1

公开(公告)日：2016-05-19

申请号：US15008325

申请日：2016-01-27

Applicant: INTEL CORPORATION

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L21/321 ,  H01L21/3105 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US20240213026A1

公开(公告)日：2024-06-27

申请号：US18085768

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Matthew J. Prince ,  Lawrence Zaino ,  Barry B. Butler ,  Girish Sharma ,  Robert R. Mitchell ,  Rajaram A. Pai ,  Niels Sveum ,  Alison V. Davis ,  Chun Chen Kuo ,  Reza Bayati ,  Swapnadip Ghosh

IPC: H01L21/28 ,  B24B37/04 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  B24B37/04 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source or drain contacts and with a top surface that is substantially coplanar with a top surface of the source or drain contacts. An example semiconductor device includes a gate structure around or otherwise on a semiconductor region and a dielectric layer present on a top surface of the gate structure. Conductive contacts are formed over source and drain regions along a source/drain contact recess or trench. The gate structure may be interrupted with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material. A top surface of the gate cut may be polished until it is substantially coplanar with a top surface of the dielectric layer over the gate structure and a top surface of the source or drain contacts.

公开(公告)号：US20240112916A1

公开(公告)日：2024-04-04

申请号：US17936934

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Matthew J. Prince ,  Alison V. Davis ,  Chun C. Kuo ,  Andrew Arnold ,  Reza Bayati

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source/drain contacts. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a source region to a drain region. Conductive contacts formed over the source and drain regions along a source/drain trench. The gate structure may be interrupted with a dielectric gate cut that further extends past the gate trench and into the source/drain trench where it can cut into one or more of the contacts. The contacts are formed before the gate cut to ensure complete fill of conductive material when forming the contacts. Accordingly, a liner structure on the conductive contacts is also broken by the intrusion of the gate cut and does not extend further up or down the sidewalls of the gate cut.

公开(公告)号：US09281401B2

公开(公告)日：2016-03-08

申请号：US14137909

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/5329 ,  H01L23/535 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了减少晶体管栅极短缺陷的技术和配置。 在一个实施例中，一种方法包括形成多条线，其中多条线中的各条线包括栅电极材料，沉积电绝缘材料以填充各线之间的区域，然后在沉积电绝缘材料之后， 至少一个独立线路的部分，以将第一晶体管器件的栅电极材料与第二晶体管器件的栅电极材料隔离。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20240203739A1

公开(公告)日：2024-06-20

申请号：US18083064

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Yulia Gotlib ,  Matthew J. Prince ,  Alison V. Davis ,  Chun Chen Kuo ,  Andrew Arnold ,  Cun Wen

IPC: H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66439 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include one or more wide gate cuts having a multi-layer dielectric structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, by any number of gate cuts that extend through an entire thickness of the gate structure and which include dielectric material. Some of the gate cuts may be at least 2× wider than others. Such wide gate cuts may include a first dielectric layer with a first material composition, a second dielectric layer on the first dielectric layer with a second material composition elementally different from the first material composition, a third dielectric layer on the second dielectric layer with a greater density than the second dielectric layer, and a dielectric fill within a remaining volume of the wide gate cut and on the third dielectric layer.