公开(公告)号：US10572260B2

公开(公告)日：2020-02-25

申请号：US15858899

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Joseph Nuzman ,  Jonas Svennebring ,  Doddaballapur N. Jayasimha ,  Samantika S. Sury ,  David A. Koufaty ,  Niall D. McDonnell ,  Yen-Cheng Liu ,  Stephen R. Van Doren ,  Stephen J. Robinson

IPC: G06F9/30 ,  G06F12/0875

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

公开(公告)号：US09875187B2

公开(公告)日：2018-01-23

申请号：US14566390

申请日：2014-12-10

Applicant: INTEL CORPORATION

Inventor： Christopher D. Bryant ,  Stephen J. Robinson

IPC: G06F12/00 ,  G06F12/0855 ,  G06F12/0802 ,  G06F9/48

CPC classification number: G06F12/0857 ,  G06F9/48 ,  G06F12/0802 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/281 ,  G06F2212/608 ,  G06F2212/65

Abstract: A first operation associated with a request for a page miss handler may be identified. A second operation associated with a current execution of the page miss handler may also be identified. An age of the first operation and an age of the second operation may be determined. The page miss handler may be interrupted based on the age of the first operation and the age of the second operation by stopping the current execution of the page miss handler for the second operation and starting execution of the page miss handler for the first operation.

公开(公告)号：US09785576B2

公开(公告)日：2017-10-10

申请号：US14227178

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Thiam Wah Loh ,  Per Hammarlund ,  Andreas Wasserbauer ,  Swee Chong Peter Kuan ,  Eckhard Delfs ,  Deepak A. Mathaikutty ,  Stephen J. Robinson ,  Gautham N. Chinya ,  Perry H. Wang ,  Chee Weng Tan ,  Hong Wang ,  Reza Fortas

IPC: G06F12/14 ,  G11C29/52 ,  G06F21/57 ,  G11C7/10 ,  G06F21/10

CPC classification number: G06F12/1408 ,  G06F12/1491 ,  G06F21/10 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/032 ,  Y02D10/13

Abstract: Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

公开(公告)号：US20150347168A1

公开(公告)日：2015-12-03

申请号：US14826351

申请日：2015-08-14

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson

IPC: G06F9/455 ,  G06F12/14

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/45533 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/206

Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括访问逻辑以确定来自虚拟机的访问请求是否是与处理器的设备相关联的设备访问页面，并且如果是，则将访问请求重新映射到虚拟设备页面 至少部分地基于存储在处理器的控制寄存器中的信息，与VM相关联的系统存储器。 描述和要求保护其他实施例。

公开(公告)号：US09141570B2

公开(公告)日：2015-09-22

申请号：US14331398

申请日：2014-07-15

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson

IPC: G06F9/48 ,  G06F9/455 ,  G06F12/14 ,  G06F13/24 ,  G06F9/30 ,  G06F12/10

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/45533 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/206

Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括访问逻辑以确定来自虚拟机的访问请求是否是与处理器的设备相关联的设备访问页面，并且如果是，则将访问请求重新映射到虚拟设备页面 至少部分地基于存储在处理器的控制寄存器中的信息，与VM相关联的系统存储器。 描述和要求保护其他实施例。

公开(公告)号：US12007938B2

公开(公告)日：2024-06-11

申请号：US17827882

申请日：2022-05-30

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson ,  Christopher D. Bryant ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F15/80

CPC classification number: G06F15/8007 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30112

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

公开(公告)号：US11347680B2

公开(公告)日：2022-05-31

申请号：US17131729

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson ,  Christopher D. Bryant ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F15/80

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

公开(公告)号：US20210117372A1

公开(公告)日：2021-04-22

申请号：US17131729

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson ,  Christopher D. Bryant ,  Jason W. Brandt

IPC: G06F15/80 ,  G06F9/30

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

公开(公告)号：US20170286113A1

公开(公告)日：2017-10-05

申请号：US15089525

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson ,  Christopher D. Bryant ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F15/80

CPC classification number: G06F15/8007 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30112

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

公开(公告)号：US09632907B2

公开(公告)日：2017-04-25

申请号：US14566374

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Beeman C. Strong ,  Stephen J. Robinson ,  Jason W. Brandt ,  Peter Lachner

IPC: G06F11/00 ,  G06F11/34 ,  G06F11/36 ,  G06F9/30

CPC classification number: G06F11/3466 ,  G06F9/30 ,  G06F11/3636

Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.