公开(公告)号：US20250006734A1

公开(公告)日：2025-01-02

申请号：US18216493

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Paul Packan ,  Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin ,  Yang Zhang ,  Chung-Hsun Lin

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit (IC) device includes a stripe of material perpendicular to, and spanning between, semiconductor structures with multiple widths, and the stripe is between transistors with channel regions of differing widths in the semiconductor structures. The material stripes cover transition portions between different widths of the semiconductor structures. The semiconductor structures may be channel structures of different types, including groups of fins or nanoribbons. Channel regions of differing widths may include more or fewer fins or narrower or wider nanoribbons. The channel regions may have alternating conductivity types, n- and p-type.

公开(公告)号：US20250006579A1

公开(公告)日：2025-01-02

申请号：US18216476

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Avijit Barik ,  Tao Chu ,  Minwoo Jang ,  Aurelia Wang ,  Conor P. Puls

IPC: H01L23/31 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417

Abstract: Devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/UV cure to remove trap charges from the semiconductor material.

公开(公告)号：US20240290788A1

公开(公告)日：2024-08-29

申请号：US18175591

申请日：2023-02-28

Applicant: Intel Corporation

Inventor： Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Robin Chao ,  David Towner ,  Orb Acton ,  Omair Saadat ,  Feng Zhang ,  Dax M. Crum ,  Yang Zhang ,  Biswajeet Guha ,  Oleg Golonzka ,  Anand S. Murthy

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.

公开(公告)号：US20240088265A1

公开(公告)日：2024-03-14

申请号：US17940194

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L29/0669 ,  H01L29/78618

Abstract: Techniques are provided herein to form semiconductor devices having epitaxial growth laterally extending between inner spacer structures to mitigate issues caused by the inner spacer structures either being too thick or too thin. A directional etch is performed along the side of a multilayer fin to create a relatively narrow opening for a source or drain region to increase the usable fin space for forming the inner spacer structures. After the inner spacer structures are formed around ends of the semiconductor layers within the fin, the exposed ends of the semiconductor layers are laterally recessed inwards from the outermost sidewalls of the inner spacer structures. Accordingly, the epitaxial source or drain region is grown from the recessed semiconductor ends and thus fills in the recessed regions between the spacer structures.

公开(公告)号：US20230307449A1

公开(公告)日：2023-09-28

申请号：US17656490

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Aurelia Chi Wang ,  Conor Puls ,  Brian Greene ,  Tofizur Rahman ,  Lin Hu ,  Jaladhi Mehta ,  Chung-Hsun Lin ,  Walid Hafez

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L29/0665 ,  H01L29/42392

Abstract: An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).

公开(公告)号：US20250107212A1

公开(公告)日：2025-03-27

申请号：US18471705

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Yang Zhang ,  Guowei Xu ,  Tao Chu ,  Robin Chao ,  Chiao-Ti Huang ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin ,  Anand Murthy

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Techniques are provided to form an integrated circuit having an airgap spacer between at least a transistor gate structure and an adjacent source or drain contact. In one such example, a FET (field effect transistor) includes a gate structure that extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between source and drain regions while the gate structure extends over the semiconductor material in a second direction. Airgaps are provided in the regions between the gate structures and the adjacent source/drain contacts. The airgaps have a low dielectric constant (e.g., around 1.0) to reduce the parasitic capacitance between the conductive structures.

公开(公告)号：US20240321887A1

公开(公告)日：2024-09-26

申请号：US18187801

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Yanbin Luo ,  Yusung Kim ,  Minwoo Jang ,  Paul Packan ,  Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Feng Zhang ,  Yang Zhang ,  Zheng Guo

IPC: H01L27/092 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L29/4966

Abstract: An IC device may have layout with reduced N-P boundary effect. The IC device may include two rows of transistors. The first row may include one or more P-type transistors. The second row may include N-type transistors. The gate electrode of a P-type transistor may include different conductive materials from the gate electrode of a N-type transistor. Each P-type transistor in the first row may be over a N-type transistor in the second row and contact the N-type transistor in the second row. For instance, the gate of the P-type transistor may contact the gate of the N-type transistor. Vacancy diffusion may occur at the boundary of the P-type transistor and the N-type transistor, causing N-P boundary effect. At least one or more other N-type transistors in the second row do not contact any P-type transistor, which can mitigate the N-P boundary effect in the IC device.

公开(公告)号：US20240321859A1

公开(公告)日：2024-09-26

申请号：US18187782

申请日：2023-03-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Paul Packan ,  Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Feng Zhang ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L27/088

Abstract: An IC device may include an array of transistors. The transistors may have separate gate electrodes. A gate electrode may include polysilicon. The gate electrodes may be separated from each other by one or more electrical insulators. The separated gate electrodes have shorter lengths, compared with connected gate electrodes, which can optimize the performance of the IC device due to local layout effect. Also, the IC device may include conductive structures crossing the support structures of multiple transistors. Such conductive structures may cause strain in the IC device, which can boost the local layout effect. The conductive structures may be insulated from a power plane. Alternatively or additionally, the IC device may include dielectric structures, which may be formed by removing gate electrodes in some of the transistors and providing a dielectric material into the openings. The presence of the dielectric structures can further boost the local layout effect.

公开(公告)号：US20240304621A1

公开(公告)日：2024-09-12

申请号：US18181598

申请日：2023-03-10

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Tao Chu ,  Robin Chao ,  Guowei Xu ,  Feng Zhang ,  Biswajeet Guha ,  Stephen M. Cea

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example fabrication method is based on patterning a foundation over which a superlattice is provided so that a single superlattice may be used to form both PMOS and NMOS stacks of nanoribbons. An example IC structure includes a support, an NMOS stack of nanoribbons stacked vertically above one another over the support, and a PMOS stack of nanoribbons stacked vertically above one another over the support, wherein at least one of the nanoribbons of the NMOS stack is vertically offset with respect to at least one of the nanoribbons of the PMOS stack.

公开(公告)号：US20240290835A1

公开(公告)日：2024-08-29

申请号：US18174007

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Guowei Xu ,  Tao Chu ,  Robin Chao ,  Jaladhi Mehta ,  Brian Greene ,  Chung-Hsun Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/78696

Abstract: Fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.