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    SEGMENTATION OF OBJECTS IN VIDEOS USING COLOR AND DEPTH INFORMATION
    11.
    发明申请
    SEGMENTATION OF OBJECTS IN VIDEOS USING COLOR AND DEPTH INFORMATION 审中-公开

    公开(公告)号：US20170372479A1

    公开(公告)日：2017-12-28

    申请号：US15190784

    申请日：2016-06-23

    Applicant: INTEL CORPORATION

    Inventor： Gowri Somanath ,  Jiajie Yao ,  Yong Jiang

    IPC: G06T7/11 ,  G06T7/136 ,  G06T5/00

    CPC classification number: G06T7/11 ,  G06T7/136 ,  G06T7/143 ,  G06T7/174 ,  G06T2207/10016 ,  G06T2207/10024 ,  G06T2207/10028 ,  G06T2207/20112

    Abstract: Techniques are provided for segmentation of objects, in videos comprising a sequence of color and depth image frames. A methodology implementing the techniques according to an embodiment includes receiving image frames, including an initial reference frame, and receiving a mask to outline a region in the reference frame that contains the object to be segmented. The method also includes calculating Gaussian mixture models associated with both the masked region and a background region external to the masked region. The method further includes segmenting the object from a current frame based on a modelling of the pixels within an active area of the current frame as a Markov Random Field of nodes for cost minimization. The costs are based in part on the Gaussian mixture models. The active area is based on the segmentation of a previous frame and on an estimation of optical flow between the previous frame and the current frame.

    Techniques for low power visual light communication
    13.
    发明授权
    Techniques for low power visual light communication 有权
    低功率视觉光通信技术

    公开(公告)号：US09191108B2

    公开(公告)日：2015-11-17

    申请号：US14128609

    申请日：2013-07-16

    Applicant: Intel Corporation

    Inventor： Yong Jiang

    IPC: G06K7/10 ,  H04B10/116

    CPC classification number: H04B10/116

    Abstract: Various embodiments are generally directed to techniques for reducing the consumption of electric power in decoding VLC frame patterns by selectively decoding data patterns based on an analysis of marker patterns. A device to receive data in visual light communications includes a processor component; and a decoding component for execution by the processor component to analyze a marker pattern of a frame pattern in a captured image to determine whether the frame pattern is a useful frame pattern, and to selectively decode a data pattern of the frame pattern to retrieve a packet of data based on the analysis. Other embodiments are described and claimed.

    Abstract translation: 各种实施例通常涉及通过基于标记图案的分析来选择性地解码数据模式来减少解码VLC帧模式中的电力消耗的技术。 在视觉光通信中接收数据的设备包括处理器组件; 以及解码部件，用于由处理器部件执行以分析捕获图像中的帧图案的标记图案，以确定所述帧模式是否是有用的帧模式，并且选择性地解码所述帧模式的数据模式以检索分组 的数据基于分析。 描述和要求保护其他实施例。

    Efficient sub-pixel disparity estimation for all sub-aperture images from densely sampled light field cameras
    15.
    发明授权
    Efficient sub-pixel disparity estimation for all sub-aperture images from densely sampled light field cameras 有权

    公开(公告)号：US11257235B2

    公开(公告)日：2022-02-22

    申请号：US17072784

    申请日：2020-10-16

    Applicant: Intel Corporation

    Inventor： Yi Wu ,  Shaojun Yao ,  Yong Jiang

    IPC: G06T7/557 ,  H04N13/271 ,  H04N13/218 ,  H04N13/00

    Abstract: A system for sub-pixel disparity estimation is described herein. The system includes memory circuitry to store image data and at least one processor to execute instructions to calculate a first disparity for a set of reference views. The reference views correspond to a first subset of views among a plurality of sub-aperture views represented in the image data. The at least one processor is to refine the first disparity to a second disparity for the reference views. The second disparity has higher precision than the first disparity. The at least one processor is to map the second disparity from the reference views to a second subset of views among the plurality of sub-aperture views different than the first subset of views.

    Real-time three-dimensional camera calibration
    16.
    发明授权
    Real-time three-dimensional camera calibration 有权

    公开(公告)号：US11210811B2

    公开(公告)日：2021-12-28

    申请号：US16339251

    申请日：2016-11-03

    Applicant: Intel Corporation

    Inventor： Yong Jiang ,  Caihong Ma ,  Xiaorui Xu ,  Mahamood Hussain

    IPC: G06T7/80 ,  G06F17/16

    Abstract: In one example, a system for real-time three-dimensional (3D) calibration includes a processor detecting mark corners at two-dimensional (2D) coordinates in an image coordinate system of an image of a specified pattern. The processor determines 3D coordinates of the mark corners in a world coordinate system based on the pattern. The 3D coordinates correspond to the 2D coordinates. The processor determines baseline depth values corresponding to original depth values for proper points on a mark plane, based on the 2D coordinates and the 3D coordinates. The processor generates a fitting model based on the baseline depth values.

    EVENT-DRIVEN FRAMEWORK FOR GPU PROGRAMMING
    17.
    发明申请
    EVENT-DRIVEN FRAMEWORK FOR GPU PROGRAMMING 审中-公开

    公开(公告)号：US20180329762A1

    公开(公告)日：2018-11-15

    申请号：US15778109

    申请日：2015-12-25

    Applicant: Intel Corporation

    Inventor： Yuanyuan Li ,  Yuting Yang ,  Yong Jiang ,  Yao Wang

    IPC: G06F9/54

    CPC classification number: G06F9/542 ,  G06F9/44 ,  G06F9/4411

    Abstract: Methods and apparatus relating to event-driven framework for GPU (Graphics Processing Unit) programming are described. In an embodiment, event-driven logic receives a signal that indicates detection of an event by a device. Memory stores information corresponding to a kernel that is to be associated with the event. The event-driven logic causes a Graphics Processing Unit (GPU) to execute the kernel to process one or more operations in response to the event. Other embodiments are also disclosed and claimed.

    APPARATUS AND METHOD TO IMPROVE MEMORY ACCESS PERFORMANCE BETWEEN SHARED LOCAL MEMORY AND SYSTEM GLOBAL MEMORY
    18.
    发明申请
    APPARATUS AND METHOD TO IMPROVE MEMORY ACCESS PERFORMANCE BETWEEN SHARED LOCAL MEMORY AND SYSTEM GLOBAL MEMORY 审中-公开

    公开(公告)号：US20170364440A1

    公开(公告)日：2017-12-21

    申请号：US15525033

    申请日：2014-12-08

    Applicant: Intel Corporation

    Inventor： Jianghong Du ,  Yong Jiang ,  Lei Shen ,  Yuanyuan Li

    IPC: G06F12/0804

    Abstract: Described is a machine-readable storage medium having instructions stored thereon, that when executed, cause a processor to perform a method which comprises: grouping two or more work groups to form a super-workgroup; and partitioning a portion of a memory space into one or more super-shared local memories (Super-SLMs), wherein the memory space shared within the super-workgroup forms at least one Super-SLM of the one or more Super-SLMs. Described is an apparatus which comprises: a plurality of execution units; a cache memory having a portion characterized as a SLM which is shared with the plurality of execution units at least one of which is to operate on a work group of a sub-slice, wherein the SLM is shared within the work group; and at least one Super-SLM for providing shared memory accessible by different work groups in the sub-slice, wherein the at least one of the execution units is to operate on the different work groups.

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