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    IGZO Devices with Reduced Electrode Contact Resistivity and Methods for Forming the Same
    11.
    发明申请
    IGZO Devices with Reduced Electrode Contact Resistivity and Methods for Forming the Same 审中-公开
    具有降低电极接触电阻率的IGZO器件及其形成方法

    公开(公告)号：US20150187958A1

    公开(公告)日：2015-07-02

    申请号：US14140768

    申请日：2013-12-26

    Applicant: Intermolecular Inc.

    Inventor： Khaled Ahmed

    IPC: H01L29/786 ,  H01L21/443 ,  H01L29/66

    CPC classification number: H01L29/78618 ,  H01L21/443 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

    Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. An IGZO channel layer is formed above the gate electrode. A contact layer is formed above the IGZO channel layer. The contact layer includes arsenic. A source electrode and a drain electrode are formed above the contact layer.

    Abstract translation: 本文所述的实施例提供诸如IGZO薄膜晶体管（TFT）的铟镓锌氧化物（IGZO）器件，以及用于形成这种器件的方法。 提供基板。 在基板上方形成栅电极。 在栅电极上方形成IGZO沟道层。 在IGZO沟道层上方形成接触层。 接触层包括砷。 源电极和漏极形成在接触层上方。

    CONTACT LAYERS FOR PHOTOVOLTAIC DEVICES
    12.
    发明申请
    CONTACT LAYERS FOR PHOTOVOLTAIC DEVICES 审中-公开
    联系层光伏器件

    公开(公告)号：US20150179839A1

    公开(公告)日：2015-06-25

    申请号：US14138555

    申请日：2013-12-23

    Applicant: Intermolecular Inc.

    Inventor： Jeroen Van Duren ,  Khaled Ahmed ,  Haifan Liang

    IPC: H01L31/0224 ,  H01L31/18

    CPC classification number: H01L31/0749 ,  H01L31/022425 ,  H01L31/0322 ,  Y02E10/541 ,  Y02P70/521

    Abstract: Solar cells and methods for forming a back contact layer for a solar cell are disclosed. The methods comprise depositing a first layer comprising a conductor on a substrate, depositing a second layer on the first layer, the second layer comprising between about 1 nm and about 25 nm of a metal chalcogenide, and forming a third layer operable as an absorber layer on the second layer. The absorber layer can comprise a photoactive semiconductor layer. In some embodiments, the absorber layer comprises a chalcogenide of copper-indium-gallium. In some embodiments, the absorber layer comprises a chalcogenide of copper-zinc-tin. In some embodiments, the absorber layer comprises CdTe. In some embodiments, the metal comprises Mo, W or Ta. In some embodiments, the metal comprises Mo. In some embodiments, the chalcogenide comprises S or Se or a combination thereof.

    Abstract translation: 公开了用于形成太阳能电池的背接触层的太阳能电池和方法。 所述方法包括在衬底上沉积包含导体的第一层，在第一层上沉积第二层，第二层包含约1nm至约25nm的金属硫族化物，以及形成可操作为吸收层的第三层 在第二层。 吸收层可以包括光敏半导体层。 在一些实施例中，吸收层包括铜铟镓的硫族化物。 在一些实施方案中，吸收层包含铜 - 锌 - 锡的硫族化物。 在一些实施例中，吸收层包括CdTe。 在一些实施方案中，金属包括Mo，W或Ta。 在一些实施方案中，金属包含Mo。在一些实施方案中，硫族化物包含S或Se或其组合。

    GATE STACKS AND OHMIC CONTACTS FOR SIC DEVICES
    13.
    发明申请
    GATE STACKS AND OHMIC CONTACTS FOR SIC DEVICES 有权
    用于SIC设备的门盖和OHMIC联系

    公开(公告)号：US20150179438A1

    公开(公告)日：2015-06-25

    申请号：US14136271

    申请日：2013-12-20

    Applicant: Intermolecular, Inc.

    Inventor： Khaled Ahmed ,  Frank Greer ,  Raj Jammy

    IPC: H01L21/02 ,  H01L29/40

    CPC classification number: H01L21/02301 ,  C23C16/0227 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/0485 ,  H01L29/66068 ,  H01L29/78

    Abstract: SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A dielectric interface layer is deposited in-situ to passivate the surface. Metal layers having a low work function are deposited above the dielectric interface layer. The stack is annealed at about 500C in forming gas to form low resistivity ohmic contacts to the SiC substrate. SiC substrates are cleaned and provided to a process chamber. In-situ plasma surface treatments are applied to further clean the surface of the substrate. A silicon oxide dielectric interface layer is deposited in-situ to passivate the surface. Optional plasma surface treatments are applied to further improve the performance of the silicon oxide dielectric interface layer. An aluminum oxide gate dielectric layer is deposited above the silicon oxide dielectric interface layer.

    Abstract translation: 将SiC衬底清洁并提供给处理室。 施加原位等离子体表面处理以进一步清洁基底的表面。 电介质界面层原位沉积以钝化表面。 具有低功函数的金属层沉积在电介质界面层的上方。 堆叠在大约500℃下在形成气体中退火以形成到SiC衬底的低电阻率欧姆接触。 将SiC衬底清洁并提供给处理室。 施加原位等离子体表面处理以进一步清洁基底的表面。 氧化硅介电界面层原位沉积以钝化表面。 施加可选的等离子体表面处理以进一步提高氧化硅介电界面层的性能。 在氧化硅介电界面层上沉积氧化铝栅极电介质层。

    Methods and Systems for Forming Reliable Gate Stack on Semiconductors
    14.
    发明申请
    Methods and Systems for Forming Reliable Gate Stack on Semiconductors 审中-公开
    在半导体上形成可靠栅极叠层的方法和系统

    公开(公告)号：US20150132938A1

    公开(公告)日：2015-05-14

    申请号：US14079410

    申请日：2013-11-13

    Applicant: Intermolecular, Inc.

    Inventor： Khaled Ahmed ,  Frank Greer

    IPC: H01L29/51 ,  H01L21/28

    CPC classification number: H01L29/517 ,  H01L21/28176 ,  H01L29/78

    Abstract: Methods are provided for the deposition of high-k gate dielectric materials which are doped with fluorine and/or nitrogen to improve the performance and reliability. The high-k dielectric materials may include at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium aluminum oxide, titanium oxide, titanium silicon oxide, or titanium aluminum oxide. The fluorine dopant is provided from a layer including titanium nitride or amorphous silicon, where the layer is doped with at least one of fluorine or nitrogen. The dopants diffuse into the high-k dielectric material during a subsequent anneal process.

    Abstract translation: 提供了用于沉积掺杂有氟和/或氮的高k栅极电介质材料以提高性能和可靠性的方法。 高k电介质材料可以包括氧化铪，氧化铪铪，氧化铪铝，氧化锆，氧化锆锆，氧化锆锆，氧化钛，氧化钛或氧化钛铝中的至少一种。 氟掺杂剂由包括氮化钛或非晶硅的层提供，其中该层掺杂有氟或氮中的至少一种。 在随后的退火过程中，掺杂剂扩散到高k电介质材料中。

    Combinatorially variable etching of stacks including two dissimilar materials for etch pit density inspection
    15.
    发明授权
    Combinatorially variable etching of stacks including two dissimilar materials for etch pit density inspection 有权
    组合可变蚀刻堆叠，包括用于蚀刻坑密度检查的两种不同材料

    公开(公告)号：US08906709B1

    公开(公告)日：2014-12-09

    申请号：US14138797

    申请日：2013-12-23

    Applicant: Intermolecular, Inc.

    Inventor： Khaled Ahmed ,  Frank Greer ,  George Mirth ,  Zhi-Wen Sun

    IPC: H01L21/66

    CPC classification number: H01L22/12 ,  H01L21/6708 ,  H01L21/67253 ,  H01L22/20

    Abstract: Provided are methods of high productivity combinatorial (HPC) inspection of semiconductor substrates. A substrate includes two layers of dissimilar materials interfacing each other, such as a stack of a silicon bottom layer and an indium gallium arsenide top layer. The dissimilar materials have one or more of thermal, structural, and lattice mismatches. As a part of the inspection, the top layer is etched in a combinatorial manner. Specifically, the top layer is divided into multiple different site-isolated regions. One such region may be etched using different process conditions from another region. Specifically, etching temperature, etching duration and/or etchant composition may vary among the site-isolated regions. After combinatorial etching, each region is inspected to determine its etch-pit density (EPD) value. These values may be then analyzed to determine an overall EPD value for the substrate, which may involve discarding EPD values for over-etched and under-etched regions.

    Abstract translation: 提供了半导体衬底的高生产率组合（HPC）检验方法。 衬底包括彼此相互接合的两层不同材料，例如硅底层和砷化铟镓顶层的叠层。 不同材料具有热，结构和晶格失配中的一种或多种。 作为检查的一部分，顶层以组合方式蚀刻。 具体来说，顶层被分成多个不同的位置隔离区域。 可以使用与另一区域不同的工艺条件来蚀刻一个这样的区域。 具体地，蚀刻温度，蚀刻持续时间和/或蚀刻剂组成可以在位置隔离区域之间变化。 在组合蚀刻之后，检查每个区域以确定其蚀刻坑密度（EPD）值。 然后可以分析这些值以确定衬底的整体EPD值，这可能涉及丢弃过蚀刻和欠蚀刻区域的EPD值。

    Methods for forming high-k dielectrics containing hafnium and zirconium using atomic layer deposition
    18.
    发明授权
    Methods for forming high-k dielectrics containing hafnium and zirconium using atomic layer deposition 有权
    使用原子层沉积形成含有铪和锆的高k电介质的方法

    公开(公告)号：US09245743B2

    公开(公告)日：2016-01-26

    申请号：US14109728

    申请日：2013-12-17

    Applicant: Intermolecular Inc.

    Inventor： Khaled Ahmed ,  Frank Greer

    IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  C23C16/40 ,  C23C16/455

    CPC classification number: H01L21/02181 ,  C23C16/405 ,  C23C16/45531 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

    Abstract: Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen.

    Abstract translation: 本文提供的实施例描述了高k电介质层和用于形成高k电介质层的方法。 提供基板。 基板包括半导体材料。 将基底暴露于铪前体。 将基底暴露于锆前体。 只有在将基底暴露于铪前体并将基底暴露于锆前体之后，才将基底暴露于氧化剂。 将衬底暴露于铪前体，将衬底暴露于锆前体，以及将衬底暴露于氧化剂引起在衬底上形成一层。 该层包括铪，锆和氧。

    Quantum Well IGZO Devices and Methods for Forming the Same
    19.
    发明申请
    Quantum Well IGZO Devices and Methods for Forming the Same 审中-公开
    量子阱IGZO器件及其形成方法

    公开(公告)号：US20150179815A1

    公开(公告)日：2015-06-25

    申请号：US14135521

    申请日：2013-12-19

    Applicant: Intermolecular, Inc.

    Inventor： Khaled Ahmed

    IPC: H01L29/786 ,  H01L29/15 ,  H01L29/66

    CPC classification number: H01L29/78696 ,  H01L29/7869 ,  H01L29/78693

    Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. An IGZO channel layer is formed above the gate electrode. The IGZO channel layer has a first sub-layer including crystalline IGZO, a second sub-layer including amorphous IGZO, and a third sub-layer including magnesium and zinc. A source electrode and a drain electrode are formed above the IGZO channel layer.

    Abstract translation: 本文所述的实施例提供诸如IGZO薄膜晶体管（TFT）的铟镓锌氧化物（IGZO）器件，以及用于形成这种器件的方法。 提供基板。 在基板上方形成栅电极。 在栅电极上方形成IGZO沟道层。 IGZO沟道层具有包括晶体IGZO的第一子层，包括非晶IGZO的第二子层和包含镁和锌的第三子层。 源电极和漏极形成在IGZO沟道层上方。

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