公开(公告)号：US20160093772A1

公开(公告)日：2016-03-31

申请号：US14501631

申请日：2014-09-30

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed ,  Frank Greer ,  Andrew Steinbach

IPC: H01L33/32 ,  H01L33/40 ,  H01L33/00

CPC classification number: H01L33/325 ,  H01L33/0062 ,  H01L33/0095 ,  H01L33/14 ,  H01L2933/0016

Abstract: Provided are methods of forming low resistivity contacts. Also provided are devices having such low resistive contacts. A method may include doping the surface of a structure, such as a gallium nitride layer. Specifically, a dopant containing layer is formed on the surface of the structure using, for example, atomic layer deposition (ALD). The dopant may magnesium. In some embodiments, the dopant containing layer also includes nitrogen. A capping layer may be then formed over the dopant containing layer to prevent dopant desorption. The stack including the structure with the dopant containing layer disposed on its surface is then annealed to transfer dopant from the dopant containing layer into the surface. After annealing, any remaining dopant containing layer is removed. When another component is later formed over the surface, a low resistivity contact is created between this other component and the doped structure.

Abstract translation: 提供形成低电阻率接触的方法。 还提供了具有这种低电阻触点的装置。 一种方法可以包括掺杂诸如氮化镓层的结构的表面。 具体地，使用例如原子层沉积（ALD）在结构的表面上形成掺杂剂层。 掺杂剂可以是镁。 在一些实施例中，含掺杂剂层还包括氮。 然后可以在含掺杂剂层上形成覆盖层以防止掺杂剂解吸。 包括具有设置在其表面上的含掺杂剂层的结构的堆叠然后被退火以将掺杂剂从掺杂剂层转移到表面中。 退火后，除去任何剩余的含掺杂剂层。 当在表面上稍后形成另一个部件时，在该另一部件与掺杂结构之间产生低电阻接触。

公开(公告)号：US09177791B2

公开(公告)日：2015-11-03

申请号：US14105871

申请日：2013-12-13

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/67 ,  C23C14/02 ,  C23C14/08 ,  C23C14/34 ,  C23C14/56 ,  C23C16/02 ,  C23C16/40 ,  C23C16/455 ,  C23C16/54

CPC classification number: H01L21/02565 ,  C23C14/021 ,  C23C14/08 ,  C23C14/081 ,  C23C14/086 ,  C23C14/34 ,  C23C14/568 ,  C23C16/0227 ,  C23C16/40 ,  C23C16/403 ,  C23C16/407 ,  C23C16/45525 ,  C23C16/54 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02658 ,  H01L21/28264 ,  H01L21/67017

Abstract: Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided. The semiconductor substrate is exposed to bromine radicals, hydrogen radicals, or a combination thereof. An oxide layer is formed above the semiconductor substrate. The semiconductor substrate is held within a controlled atmosphere at least from the completion of the exposing of the semiconductor substrate to bromine radicals, hydrogen radicals, or a combination thereof and the beginning of the forming of the oxide layer.

Abstract translation: 本文提供的实施例描述了用于形成半导体器件的系统和方法。 提供半导体衬底。 半导体衬底暴露于溴自由基，氢自由基或其组合。 在半导体衬底的上方形成氧化物层。 半导体衬底至少从半导体衬底暴露于溴自由基，氢自由基或其组合的完成而保持在受控气氛中，并且开始形成氧化物层。

公开(公告)号：US20150179773A1

公开(公告)日：2015-06-25

申请号：US14135534

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. A gate dielectric layer is formed above the gate electrode. An interface layer is formed above the gate dielectric material. An IGZO channel layer is formed above the interface layer. A source electrode and a drain electrode are formed above the IGZO channel layer. The interface layer includes a material different than that of the gate dielectric layer and the IGZO channel layer.

Abstract translation: 本文所述的实施例提供诸如IGZO薄膜晶体管（TFT）的铟镓锌氧化物（IGZO）器件，以及用于形成这种器件的方法。 提供基板。 在基板上方形成栅电极。 栅极电介质层形成在栅电极上。 界面层形成在栅极电介质材料上方。 在界面层的上方形成IGZO沟道层。 源电极和漏极形成在IGZO沟道层上方。 界面层包括与栅极电介质层和IGZO沟道层不同的材料。

公开(公告)号：US20150171227A1

公开(公告)日：2015-06-18

申请号：US14133521

申请日：2013-12-18

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/26

CPC classification number: H01L29/78693 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02538 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02631 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. An IGZO channel layer is formed above the gate electrode. The IGZO channel layer has a first sub-layer including c-IGZO and a second sub-layer including a-IGZO. A source electrode and a drain electrode are formed above the IGZO channel layer.

Abstract translation: 本文所述的实施例提供诸如IGZO薄膜晶体管（TFT）的铟镓锌氧化物（IGZO）器件，以及用于形成这种器件的方法。 提供基板。 在基板上方形成栅电极。 在栅电极上方形成IGZO沟道层。 IGZO沟道层具有包括c-IGZO的第一子层和包括-IGZO的第二子层。 源电极和漏极形成在IGZO沟道层上方。

公开(公告)号：US08975706B2

公开(公告)日：2015-03-10

申请号：US14135381

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed ,  Frank Greer

IPC: H01L21/28 ,  H01L27/092

CPC classification number: H01L21/28158 ,  H01L21/0215 ,  H01L21/0228 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation.

Abstract translation: 提供场效应晶体管（FET）组件及其形成方法。 FET组件可以包括由钽氧化硅形成并且具有小于5％的硅与钽和硅（Si /（Ta + Si））的原子比的介电层以提供低陷阱密度。 电介质层可以设置在界面层上，该界面层设置在沟道区域上。 可以使用相同类型的电介质层的nMOSFET（例如，III-V材料）和pMOSFET（例如，锗）的公共栅极电介质。 沟道区可以包括砷化铟镓，磷酸铟或锗中的一种。 界面层可以包括氧化硅以提供更高的能量势垒。 可以使用原子层沉积技术，通过在沉积表面上吸附含有钽和硅的两种前体，然后在相同的操作中氧化两种前体来形成电介质层。

公开(公告)号：US20150255332A1

公开(公告)日：2015-09-10

申请号：US14721248

申请日：2015-05-26

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L21/768 ,  H01L21/66

CPC classification number: H01L21/76864 ,  H01L21/02005 ,  H01L21/02104 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/3065 ,  H01L22/12 ,  H01L22/14 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14698 ,  H01L29/1606 ,  H01L29/41 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/786

Abstract: Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10−9 Ω·cm2.

Abstract translation: 公开了半导体器件的接触件及其制造方法。 一种方法包括在半导体上形成第一层，第一层包括一种或多种金属; 在所述第一层上形成第二层，所述第二层包含所述一种或多种金属，氮和氧; 以及加热所述第一层和所述第二层，使得氧从所述第二层迁移到所述第一层中，并且所述第一层在加热后包括亚化学计量的金属氧化物。 示例性实施例在第一层中使用诸如Ti之类的过渡金属。 在加热之后，在金属氮化物导体和半导体之间存在约2.5nm厚度的亚化学计量氧化层。 比接触电阻率小于约7×10-9＆OHgr·cm2。

公开(公告)号：US20150155368A1

公开(公告)日：2015-06-04

申请号：US14095834

申请日：2013-12-03

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L29/66

CPC classification number: H01L29/66765 ,  H01L29/458 ,  H01L29/78618 ,  H01L29/78669

Abstract: Embodiments described herein provide amorphous silicon thin-film transistors (a-Si TFTs) and methods for forming a-Si TFTs. A substrate is provided. A gate electrode is formed above the substrate. An a-Si channel layer is formed above the gate electrode. A contact layer is formed above the a-Si channel layer. The contact layer includes titanium, zinc, arsenic, or a combination thereof. A source electrode and a drain electrode are formed above the contact layer.

Abstract translation: 本文描述的实施例提供非晶硅薄膜晶体管（a-Si TFT）以及用于形成a-Si TFT的方法。 提供基板。 在基板上方形成栅电极。 在栅电极上方形成a-Si沟道层。 在a-Si沟道层上形成接触层。 接触层包括钛，锌，砷或其组合。 源电极和漏极形成在接触层上方。

公开(公告)号：US20150035085A1

公开(公告)日：2015-02-05

申请号：US14109728

申请日：2013-12-17

Applicant: Intermolecular Inc.

Inventor： Khaled Ahmed ,  Frank Greer

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/02181 ,  C23C16/405 ,  C23C16/45531 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/517

Abstract: Embodiments provided herein describe high-k dielectric layers and methods for forming high-k dielectric layers. A substrate is provided. The substrate includes a semiconductor material. The substrate is exposed to a hafnium precursor. The substrate is exposed to a zirconium precursor. The substrate is exposed to an oxidant only after the exposing of the substrate to the hafnium precursor and the exposing of the substrate to the zirconium precursor. The exposing of the substrate to the hafnium precursor, the exposing of the substrate to the zirconium precursor, and the exposing of the substrate to the oxidant causes a layer to be formed over the substrate. The layer includes hafnium, zirconium, and oxygen.

Abstract translation: 本文提供的实施例描述了高k电介质层和用于形成高k电介质层的方法。 提供基板。 基板包括半导体材料。 将基底暴露于铪前体。 将基底暴露于锆前体。 只有在将基底暴露于铪前体并将基底暴露于锆前体之后，才将基底暴露于氧化剂。 将衬底暴露于铪前体，将衬底暴露于锆前体，以及将衬底暴露于氧化剂引起在衬底上形成一层。 该层包括铪，锆和氧。

公开(公告)号：US20140264825A1

公开(公告)日：2014-09-18

申请号：US14135431

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L21/283 ,  H01L29/41

CPC classification number: H01L21/76864 ,  H01L21/02005 ,  H01L21/02104 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/3065 ,  H01L22/12 ,  H01L22/14 ,  H01L27/1462 ,  H01L27/14643 ,  H01L27/14698 ,  H01L29/1606 ,  H01L29/41 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/778 ,  H01L29/786

Abstract: Contacts for semiconductor devices and methods of making thereof are disclosed. A method comprises forming a first layer on a semiconductor, the first layer comprising one or more metals; forming a second layer on the first layer, the second layer comprising the one or more metals, nitrogen and oxygen; and heating the first and second layer such that oxygen migrates from the second layer into the first layer and the first layer comprises a sub-stoichiometric metal oxide after heating. Exemplary embodiments use transition metals such as Ti in the first layer. After heating there is a sub-stoichiometric oxide layer of about 2.5 nm thickness between a metal nitride conductor and the semiconductor. The specific contact resistivity is less than about 7×10−9 Ω·cm2.

Abstract translation: 公开了半导体器件的接触件及其制造方法。 一种方法包括在半导体上形成第一层，第一层包括一种或多种金属; 在所述第一层上形成第二层，所述第二层包含所述一种或多种金属，氮和氧; 以及加热所述第一层和所述第二层，使得氧从所述第二层迁移到所述第一层中，并且所述第一层在加热后包括亚化学计量的金属氧化物。 示例性实施例在第一层中使用诸如Ti之类的过渡金属。 在加热之后，在金属氮化物导体和半导体之间存在约2.5nm厚度的亚化学计量氧化层。 比接触电阻率小于约7×10-9＆OHgr·cm2。

公开(公告)号：US09082793B1

公开(公告)日：2015-07-14

申请号：US14135534

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Khaled Ahmed

IPC: H01L29/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: Embodiments described herein provide indium-gallium-zinc oxide (IGZO) devices, such as IGZO thin-film transistors (TFTs), and methods for forming such devices. A substrate is provided. A gate electrode is formed above the substrate. A gate dielectric layer is formed above the gate electrode. An interface layer is formed above the gate dielectric material. An IGZO channel layer is formed above the interface layer. A source electrode and a drain electrode are formed above the IGZO channel layer. The interface layer includes a material different than that of the gate dielectric layer and the IGZO channel layer.

Abstract translation: 本文所述的实施例提供诸如IGZO薄膜晶体管（TFT）的铟镓锌氧化物（IGZO）器件，以及用于形成这种器件的方法。 提供基板。 在基板上方形成栅电极。 栅极电介质层形成在栅电极上。 界面层形成在栅极电介质材料上方。 在界面层的上方形成IGZO沟道层。 源电极和漏极形成在IGZO沟道层上方。 界面层包括与栅极电介质层和IGZO沟道层不同的材料。