Selective epitaxial silicon for intrinsic-extrinsic base link
    11.
    发明授权
    Selective epitaxial silicon for intrinsic-extrinsic base link 失效
    用于内在 - 外在基极连接的选择性外延硅

    公开(公告)号:US5420454A

    公开(公告)日:1995-05-30

    申请号:US269992

    申请日:1994-07-01

    CPC分类号: H01L29/66287 H01L29/1004

    摘要: In a bipolar device, selective epitaxial silicon provides an improved intrinsic-extrinsic base link. A trench physically separates an intrinsic and extrinsic base portion. The trench includes sidewalls having a thin oxide layer formed thereon. The bottom of the trench is exposed during processing. A shallow link between the intrinsic-extrinsic regions of a bipolar transistor base is formed by depositing a heavily boron doped layer of silicon on the exposed portion of the trench. During subsequent processing, including rapid thermal anneal, there is some boron out-diffusion which forms a shallow diffused intrinsic-extrinsic base link.

    摘要翻译: 在双极器件中,选择性外延硅提供了改进的本征 - 外在基极连接。 沟槽物理地分离固有和非本征基部分。 沟槽包括其上形成有薄氧化物层的侧壁。 沟槽的底部在加工过程中暴露。 通过在沟槽的暴露部分上沉积重硼掺杂的硅层来形成双极晶体管基极的本征 - 非本征区域之间的浅连接。 在随后的处理过程中,包括快速热退火,有一些硼外扩散形成了浅扩散的固有 - 外在基极。

    Reducing dust contamination in optical mice
    12.
    发明授权
    Reducing dust contamination in optical mice 有权
    减少光学鼠标中的灰尘污染

    公开(公告)号:US07940247B2

    公开(公告)日:2011-05-10

    申请号:US10903830

    申请日:2004-07-30

    申请人: Dietrich W. Vook

    发明人: Dietrich W. Vook

    IPC分类号: G09G5/08

    CPC分类号: G06F3/0317 G06F3/03543

    摘要: Reduction of dust contamination in optical mice. Trapped charged particles within an optical element result in a surface charge on the optical element, the surface charge reducing the attraction of dust to the optical surface. Charged particles may be trapped in the optical element, or in a coating on the element. Irradiation from an alpha source or ion implantation techniques may be used.

    摘要翻译: 减少光学鼠标中的粉尘污染。 光学元件内的被捕获的带电粒子导致光学元件上的表面电荷,表面电荷减少了灰尘对光学表面的吸引力。 带电粒子可以被捕获在光学元件中,或者在元件上的涂层中。 可以使用从α源或离子注入技术的照射。

    Method of fabricating and a device that includes nanosize pores having well controlled geometries
    13.
    发明授权
    Method of fabricating and a device that includes nanosize pores having well controlled geometries 失效
    制造方法和包括具有良好控制几何形状的纳米尺度孔的装置

    公开(公告)号:US06706204B2

    公开(公告)日:2004-03-16

    申请号:US10027598

    申请日:2001-12-19

    IPC分类号: H01L2100

    摘要: A method of fabricating nanosized holes with controlled geometries employs tools and methods developed in the microelectronics industry. The method exploits the fact that epitaxially grown film thicknesses can be controlled within a few atomic monolayers and that by using etching techniques, trenches and channels can be created that are only a few nanometers wide. The method involves bonding two shallow channels at an angle such that a nanopore is defined by the intersection. Thus, a nanopore-defining device includes a nanopore with dimensions that are determined by the dimensions and orientations of the intersecting channels, with the dimensions being accurately controlled within a few monolayers.

    摘要翻译: 制造具有受控几何形状的纳米孔的方法采用在微电子工业中开发的工具和方法。 该方法利用了外延生长的膜厚度可以控制在几个原子单层内的事实,并且通过使用蚀刻技术,可以产生只有几纳米宽的沟槽和沟道。 该方法包括以一定角度键合两个浅沟道,使得纳米孔由交点定义。 因此,纳米孔限定装置包括具有由相交通道的尺寸和取向决定的尺寸的纳米孔,其尺寸被准确地控制在几个单层内。

    Integrated circuit device providing isolation between adjacent regions

    公开(公告)号:US06437379B1

    公开(公告)日:2002-08-20

    申请号:US09863854

    申请日:2001-05-22

    IPC分类号: H01L31062

    摘要: A fabrication method for providing isolation between adjacent regions of an integrated circuit includes providing a guard layer over field edges that are the interfaces between field oxide regions and diffusion regions in which dopant is introduced. The guard layer will inhibit introduction of dopant along the field-edge, so that a substantially dopant-free transition strip is formed. The transition strip inhibits current leakage from the active region to the field oxide region. In one embodiment, the active region is an active area diode, such as used to form an Active Pixel Sensor (APS) pixel. The guard layer is biased so as to further inhibit current leakage during circuit operation. In another embodiment, the method is used in the fabrication of transistors for APS pixels having an overlay photodiode structure.

    Camera module with focus adjustment structure and systems and methods of making the same
    17.
    发明授权
    Camera module with focus adjustment structure and systems and methods of making the same 有权
    具有焦点调整结构的相机模块和制作相同的系统和方法

    公开(公告)号:US07330211B2

    公开(公告)日:2008-02-12

    申请号:US10615622

    申请日:2003-07-08

    IPC分类号: H04N5/225

    CPC分类号: H04N5/2254

    摘要: Camera modules with focus adjustment structures and systems and methods of making the same are described. In one aspect, a sensor housing having an image sensor, a lens holder comprising a lens, and a deformable focus adjustment structure are provided. The focus adjustment structure is deformed to move the lens whereby light is focused onto the image sensor.

    摘要翻译: 描述了具有焦点调整结构和系统的相机模块及其制造方法。 在一个方面,提供了一种具有图像传感器的传感器壳体,包括透镜的透镜夹持器和可变形聚焦调节结构。 焦点调整结构变形以移动透镜,由此光聚焦到图像传感器上。

    Isolation of alpha silicon diode sensors through ion implantation
    19.
    发明授权
    Isolation of alpha silicon diode sensors through ion implantation 失效
    通过离子注入隔离α硅二极管传感器

    公开(公告)号:US06759724B2

    公开(公告)日:2004-07-06

    申请号:US10349447

    申请日:2003-01-22

    IPC分类号: H01L3120

    CPC分类号: H01L27/14601 H01L27/14665

    摘要: An image sensor. The image sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. An amorphous silicon electrode layer is adjacent to the interconnect structure. The amorphous silicon electrode layer includes electrode ion implantation regions between pixel electrode regions. The pixel electrode regions define cathodes of an array of image sensors. The electrode ion implantation regions provide physical isolation between the pixel electrode regions. The cathodes are electrically connected to the interconnect structure. An amorphous silicon I-layer is adjacent to the amorphous silicon electrode layer. The amorphous silicon I-layer forms an inner layer of each of the image sensors. A transparent electrode layer is formed adjacent to the image sensors. An inner surface of the transparent electrode is electrically connected to anodes of the image sensors and the interconnect structure. The amorphous silicon I-layer region can further include I-layer ion implantation regions that provide physical isolation between the inner layers of the image sensors. The I-layer ion implantation regions align with the electrode ion implantation regions. An amorphous silicon P-layer can be formed adjacent to the amorphous silicon I-layer. The amorphous silicon P-layer forms an outer layer of each of the image sensors. The amorphous silicon P-layer region can include P-layer ion implantation regions that provide physical isolation between the outer layers of the image sensors.

    摘要翻译: 图像传感器。 图像传感器阵列包括基板。 在衬底附近形成互连结构。 非晶硅电极层与互连结构相邻。 非晶硅电极层包括像素电极区域之间的电极离子注入区域。 像素电极区域限定图像传感器阵列的阴极。 电极离子注入区域提供像素电极区域之间的物理隔离。 阴极电连接到互连结构。 非晶硅I层与非晶硅电极层相邻。 非晶硅I层形成每个图像传感器的内层。 形成与图像传感器相邻的透明电极层。 透明电极的内表面电连接到图像传感器和互连结构的阳极。 非晶硅I层区域还可以包括在图像传感器的内层之间提供物理隔离的I层离子注入区域。 I层离子注入区域与电极离子注入区域对准。 非晶硅P层可以与非晶硅I层相邻地形成。 非晶硅P层形成每个图像传感器的外层。 非晶硅P层区域可以包括在图像传感器的外层之间提供物理隔离的P层离子注入区域。

    Conductive guard rings for elevated active pixel sensors
    20.
    发明授权
    Conductive guard rings for elevated active pixel sensors 有权
    导电保护环用于升高的有源像素传感器

    公开(公告)号:US06229191B1

    公开(公告)日:2001-05-08

    申请号:US09443960

    申请日:1999-11-19

    IPC分类号: H01L310376

    CPC分类号: H01L27/14643 H01L27/14632

    摘要: An array of active pixel sensors. The array of active pixel sensors includes a substrate that includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes a plurality of conductive vias. A plurality of conductive guard rings are formed adjacent to the interconnect structure. Each conductive guard ring is electrically connected to the substrate through at least one of the conductive vias. A plurality of photo diode sensors are formed adjacent to the interconnect structure. Each photo diode sensor is surrounded by at least one of the conductive guard rings. Each photo diode sensor includes a pixel electrode. The pixel electrode is electrically connected to the substrate through a corresponding conductive via. An I-layer is formed adjacent to the pixel electrode. The array of active pixel sensors further includes a transparent conductive layer formed adjacent to the photo diode sensors. An inner surface of the conductive layer is physically connected to the photo diode sensors, and electrically connected to the substrate through a conductive via. The electronic circuitry biases the photo diode sensors and controls a guard voltage potential of the conductive guard rings.

    摘要翻译: 一组有源像素传感器。 有源像素传感器的阵列包括包括电子电路的衬底。 在衬底附近形成互连结构。 互连结构包括多个导电通孔。 在互连结构附近形成多个导电保护环。 每个导电保护环通过至少一个导电通孔与衬底电连接。 在互连结构附近形成多个光电二极管传感器。 每个光电二极管传感器被至少一个导电保护环包围。 每个光电二极管传感器包括像素电极。 像素电极通过相应的导电通孔电连接到衬底。 在像素电极附近形成I层。 有源像素传感器阵列还包括邻近光电二极管传感器形成的透明导电层。 导电层的内表面物理地连接到光电二极管传感器,并且通过导电通孔与衬底电连接。 电子电路偏置光电二极管传感器并控制导电保护环的保护电压电位。