公开(公告)号：US06215164B1

公开(公告)日：2001-04-10

申请号：US09361342

申请日：1999-07-26

申请人： Min Cao ,  Jeremy A Theil ,  Gary W Ray ,  Dietrich W Vook ,  Shawming Ma

发明人： Min Cao ,  Jeremy A Theil ,  Gary W Ray ,  Dietrich W Vook ,  Shawming Ma

IPC分类号： A01L2714

CPC分类号： H01L27/14634 ,  H01L27/14603 ,  H01L27/14636 ,  H01L2224/48463

摘要： An image pixel sensor array. The image pixel sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. A plurality of image pixel sensors are formed adjacent to the interconnect structure. Each image pixel sensor includes a pixel electrode, and an I-layer formed adjacent to the pixel electrode. The I-layer includes a first surface adjacent to the pixel electrode, and a second surface opposite the first surface. The first surface includes a first surface area which is less than a second surface area of the second surface. The image pixel sensor array further includes an insulating material between each image pixel sensor, and a transparent electrode formed over the image pixel sensors. The transparent electrode electrically connects the image pixel sensors and the interconnect structure.

摘要翻译： 图像像素传感器阵列。 图像像素传感器阵列包括基板。 在衬底附近形成互连结构。 在互连结构附近形成多个图像像素传感器。 每个图像像素传感器包括像素电极和与像素电极相邻形成的I层。 I层包括与像素电极相邻的第一表面和与第一表面相对的第二表面。 第一表面包括小于第二表面的第二表面积的第一表面区域。 图像像素传感器阵列还包括在每个图像像素传感器和形成在图像像素传感器之上的透明电极之间的绝缘材料。 透明电极电连接图像像素传感器和互连结构。

公开(公告)号：US6018187A

公开(公告)日：2000-01-25

申请号：US174718

申请日：1998-10-19

申请人： Jeremy A. Theil ,  Min Cao ,  Dietrich W. Vook ,  Frederick A. Perner ,  Xin Sun ,  Shawming Ma ,  Gary W. Ray

发明人： Jeremy A. Theil ,  Min Cao ,  Dietrich W. Vook ,  Frederick A. Perner ,  Xin Sun ,  Shawming Ma ,  Gary W. Ray

IPC分类号： H04N5/335 ,  H01L27/146 ,  H01L31/02 ,  H01L31/00 ,  H01L31/075 ,  H01L31/105 ,  H01L31/117

CPC分类号： H01L27/14632 ,  H01L27/14643 ,  H01L31/02002

摘要： An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. Each photo sensor includes an individual pixel electrode. An I-layer is formed over all of the pixel electrodes. A transparent electrode is formed over the I-layer. An inner surface of the transparent electrode is electrically connected to the I-layer and the interconnect structure.

摘要翻译： 有源像素传感器。 有源像素传感器包括衬底，与衬底相邻的互连结构以及与互连结构相邻的至少一个光电传感器。 每个光传感器包括单独的像素电极。 在所有像素电极上形成I层。 在I层上形成透明电极。 透明电极的内表面与I层和互连结构电连接。

公开(公告)号：US6114739A

公开(公告)日：2000-09-05

申请号：US174717

申请日：1998-10-19

申请人： Jeremy A. Theil ,  Min Cao ,  Dietrich W. Vook ,  Frederick A. Perner ,  Xin Sun ,  Shawming Ma ,  Gary W. Ray ,  Wayne M. Greene ,  Kit M. Cham ,  Steven A. Lupi

发明人： Jeremy A. Theil ,  Min Cao ,  Dietrich W. Vook ,  Frederick A. Perner ,  Xin Sun ,  Shawming Ma ,  Gary W. Ray ,  Wayne M. Greene ,  Kit M. Cham ,  Steven A. Lupi

IPC分类号： H01L27/146 ,  H01L31/02 ,  H01L27/14 ,  H01L31/00

CPC分类号： H01L27/14643 ,  H01L27/14632 ,  H01L31/02005

摘要： An active pixel sensor. The active pixel sensor includes a substrate, an interconnect structure adjacent to the substrate, and at least one photo sensor adjacent to the interconnect structure. At least one photo sensor is formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode which includes a patterned doped semiconductor layer. An I-layer is formed adjacent to the patterned doped semiconductor layer. A transparent electrode is formed adjacent to the I-layer. A method of forming the active pixel sensor includes forming an interconnect structure over a substrate. Next, a doped semiconductor layer is deposited over the interconnect structure. The doped semiconductor layer is etched forming pixel electrode. An I-layer is deposited over the pixel electrodes. Finally, a transparent conductive layer is deposited over the I-layer.

摘要翻译： 有源像素传感器。 有源像素传感器包括衬底，与衬底相邻的互连结构以及与互连结构相邻的至少一个光电传感器。 在互连结构附近形成至少一个光电传感器。 每个光传感器包括包括图案化掺杂半导体层的像素电极。 在图案化掺杂半导体层附近形成I层。 形成与I层相邻的透明电极。 形成有源像素传感器的方法包括在衬底上形成互连结构。 接下来，在互连结构上沉积掺杂半导体层。 蚀刻形成像素电极的掺杂半导体层。 I层沉积在像素电极上。 最后，透明导电层沉积在I层上。

公开(公告)号：US06016011A

公开(公告)日：2000-01-18

申请号：US300812

申请日：1999-04-27

申请人： Min Cao ,  Jeremy A Theil ,  Gary W Ray ,  Dietrich W Vook

发明人： Min Cao ,  Jeremy A Theil ,  Gary W Ray ,  Dietrich W Vook

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L31/10 ,  H01L31/105 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L31/1055 ,  H01L21/76804 ,  H01L21/76807 ,  H01L23/5226 ,  H01L21/7684 ,  H01L2924/0002

摘要： A dual-inlaid damascene contact having a polished surface for directly communicating an electrically conductive layer to a semiconductor layer. A dielectric layer is formed on the electrically conductive layer. A dual-inlaid cavity is formed by etching a via cavity and a contact cavity into the dielectric layer. A damascene contact is formed by depositing tungsten into the dual-inlaid cavity. Chemical-mechanical polishing is used to planarize and smooth a surface of the damascene contact until the surface is coplanar with the dielectric layer. A semiconductor layer is then deposited on the damascene contact. The semiconductor layer can be the node of an amorphous silicon P-I-N photodiode. Electrical interconnection between the node of the photodiode and the electrically conductive layer is accomplished without using an intermediate electrode, and the smooth damascene contact improves surface adhesion, reduces contact resistance, and provides a discrete connection to the semiconductor layer. The damascene contact may be polished to provide a light reflective surface finish for reflecting light incident on the damascene contact back into the semiconductor layer to improve the quantum efficiency of the P-I-N photodiode.

摘要翻译： 具有抛光表面的双镶嵌镶嵌接触件，用于将导电层直接连接到半导体层。 在导电层上形成电介质层。 通过将通孔和接触腔蚀刻到电介质层中形成双嵌入腔。 通过将钨沉积到双镶嵌空腔中形成镶嵌接触。 化学机械抛光用于平坦化和平滑镶嵌接触面，直到表面与介电层共面。 然后将半导体层沉积在镶嵌接触件上。 半导体层可以是非晶硅P-I-N光电二极管的节点。 在不使用中间电极的情况下实现光电二极管的节点与导电层之间的电气互连，并且光滑的镶嵌接触改善了表面粘附性，降低了接触电阻，并提供了与半导体层的离散连接。 可以抛光镶嵌接触以提供光反射表面光洁度，以将入射到镶嵌触点的光反射回半导体层，以提高P-I-N光电二极管的量子效率。

公开(公告)号：US06586812B1

公开(公告)日：2003-07-01

申请号：US09290443

申请日：1999-04-13

申请人： Min Cao ,  Jeremy A. Theil ,  Gary W. Ray ,  Dietrich W. Vook

发明人： Min Cao ,  Jeremy A. Theil ,  Gary W. Ray ,  Dietrich W. Vook

IPC分类号： H01L3120

CPC分类号： H01L27/14601 ,  H01L27/14665

摘要： An array of image sensors that includes ion implantation regions that provide physical isolation between the pixel electrode regions. The physical isolation reduces coupling and cross-talk between the image sensors. The array of isolated image sensors can be formed by a simple fabrication process.

摘要翻译： 包括在像素电极区域之间提供物理隔离的离子注入区域的图像传感器阵列。 物理隔离减少了图像传感器之间的耦合和串扰。 隔离图像传感器的阵列可以通过简单的制造工艺形成。

公开(公告)号：US06759724B2

公开(公告)日：2004-07-06

申请号：US10349447

申请日：2003-01-22

申请人： Min Cao ,  Jeremy A. Theil ,  Gary W. Ray ,  Dietrich W. Vook

发明人： Min Cao ,  Jeremy A. Theil ,  Gary W. Ray ,  Dietrich W. Vook

IPC分类号： H01L3120

CPC分类号： H01L27/14601 ,  H01L27/14665

摘要： An image sensor. The image sensor array includes a substrate. An interconnect structure is formed adjacent to the substrate. An amorphous silicon electrode layer is adjacent to the interconnect structure. The amorphous silicon electrode layer includes electrode ion implantation regions between pixel electrode regions. The pixel electrode regions define cathodes of an array of image sensors. The electrode ion implantation regions provide physical isolation between the pixel electrode regions. The cathodes are electrically connected to the interconnect structure. An amorphous silicon I-layer is adjacent to the amorphous silicon electrode layer. The amorphous silicon I-layer forms an inner layer of each of the image sensors. A transparent electrode layer is formed adjacent to the image sensors. An inner surface of the transparent electrode is electrically connected to anodes of the image sensors and the interconnect structure. The amorphous silicon I-layer region can further include I-layer ion implantation regions that provide physical isolation between the inner layers of the image sensors. The I-layer ion implantation regions align with the electrode ion implantation regions. An amorphous silicon P-layer can be formed adjacent to the amorphous silicon I-layer. The amorphous silicon P-layer forms an outer layer of each of the image sensors. The amorphous silicon P-layer region can include P-layer ion implantation regions that provide physical isolation between the outer layers of the image sensors.

摘要翻译： 图像传感器。 图像传感器阵列包括基板。 在衬底附近形成互连结构。 非晶硅电极层与互连结构相邻。 非晶硅电极层包括像素电极区域之间的电极离子注入区域。 像素电极区域限定图像传感器阵列的阴极。 电极离子注入区域提供像素电极区域之间的物理隔离。 阴极电连接到互连结构。 非晶硅I层与非晶硅电极层相邻。 非晶硅I层形成每个图像传感器的内层。 形成与图像传感器相邻的透明电极层。 透明电极的内表面电连接到图像传感器和互连结构的阳极。 非晶硅I层区域还可以包括在图像传感器的内层之间提供物理隔离的I层离子注入区域。 I层离子注入区域与电极离子注入区域对准。 非晶硅P层可以与非晶硅I层相邻地形成。 非晶硅P层形成每个图像传感器的外层。 非晶硅P层区域可以包括在图像传感器的外层之间提供物理隔离的P层离子注入区域。

公开(公告)号：US06387736B1

公开(公告)日：2002-05-14

申请号：US09299687

申请日：1999-04-26

申请人： Min Cao ,  Jeremy A Theil ,  Gary W Ray ,  Dietrich W Vook

发明人： Min Cao ,  Jeremy A Theil ,  Gary W Ray ,  Dietrich W Vook

IPC分类号： H01L2100

CPC分类号： H01L21/0242 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/2007

摘要： A structure and a method for providing structural stability at an interface between two poorly adhering layers in a semiconductor device involve providing anchoring channels in one of the poorly adhering layers through which the other poorly adhering layer can be anchored to a third layer. Specifically, the structure and method are applicable to a three-layer stack having a top layer of amorphous silicon, a middle layer of titanium nitride, and a bottom layer of oxide. In order to reduce susceptibility to delamination between the amorphous silicon layer and the titanium nitride layer, the anchoring channels are created in the titanium nitride layer to allow the amorphous silicon to attach to the oxide layer. Because the amorphous silicon layer and the oxide layer exhibit good adhesion between each other, delamination between the amorphous silicon layer and the titanium nitride layer is minimized.

摘要翻译： 在半导体器件中的两个不良粘合层之间的界面处提供结构稳定性的结构和方法包括在不良粘合层之一提供锚定通道，另一个不良粘附层可以通过该沟槽固定到第三层。 具体地说，该结构和方法适用于具有非晶硅顶层，氮化钛中间层和氧化物底层的三层堆叠。 为了降低对非晶硅层和氮化钛层之间的分层的敏感性，在氮化钛层中产生锚定通道，以使非晶硅附着在氧化物层上。 由于非晶硅层和氧化物层彼此之间表现出良好的粘合性，所以非晶硅层和氮化钛层之间的分层最小化。

公开(公告)号：US06396118B1

公开(公告)日：2002-05-28

申请号：US09496941

申请日：2000-02-03

申请人： Jeremy A. Theil ,  Jane Mei-Jech Lin ,  Min Cao ,  Gary W. Ray ,  Shawming Ma ,  Xin Sun

发明人： Jeremy A. Theil ,  Jane Mei-Jech Lin ,  Min Cao ,  Gary W. Ray ,  Shawming Ma ,  Xin Sun

IPC分类号： H01L3100

CPC分类号： H01L27/14665 ,  H01L27/14601 ,  H01L31/022408

摘要： An array of active pixel sensors includes a substrate. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes a plurality of conductive vias. A plurality of photo sensors are formed adjacent to the interconnect structure. Each photo sensor includes a pixel electrode. Each pixel electrode is electrically connected to the substrate through a corresponding conductive yet. A I-layer is formed over each of the pixel electrodes. The array of active pixel sensors further includes a conductive mesh formed adjacent to the photo sensors. An inner surface of the conductive mesh is electrically and physically connected to the photo sensors, and electrically connected to the substrate through a conductive via. The conductive mesh providing light shielding between photo sensors thereby reducing cross-talk between the photo sensors. The conductive mesh includes apertures that align with at least one of the pixel electrodes of the photo sensors.

摘要翻译： 有源像素传感器的阵列包括衬底。 在衬底附近形成互连结构。 互连结构包括多个导电通孔。 在互连结构附近形成多个光传感器。 每个光传感器包括像素电极。 每个像素电极通过相应的导电性电连接到基板。 在每个像素电极上形成I层。 有源像素传感器阵列还包括邻近光传感器形成的导电网。 导电网的内表面电学上和物理地连接到光传感器，并且通过导电通孔电连接到基板。 导电网提供光传感器之间的光屏蔽，从而减少光传感器之间的串扰。 导电网包括与光传感器的至少一个像素电极对准的孔。

公开(公告)号：US6051867A

公开(公告)日：2000-04-18

申请号：US306238

申请日：1999-05-06

申请人： Jeremy A. Theil ,  Gary W. Ray ,  Frederick A. Perner ,  Min Cao

发明人： Jeremy A. Theil ,  Gary W. Ray ,  Frederick A. Perner ,  Min Cao

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L27/146 ,  H01L31/02 ,  H01L33/00

CPC分类号： H01L27/14601 ,  H01L31/02005

摘要： An integrated circuit sensor structure. The integrated circuit sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A dielectric layer is adjacent to the interconnect structure. The dielectric layer includes a planar surface, and conductive dielectric vias which pass through the dielectric layer and are electrically connected to the interconnect vias. The dielectric layer further includes an interlayer planarization dielectric layer adjacent to the interconnect structure, and a passivating layer adjacent to the interlayer planarization dielectric layer. The integrated circuit sensor structure further includes sensors adjacent to the dielectric layer. The interconnect vias and the dielectric vias electrically connect the electronic circuitry to the sensors.

摘要翻译： 集成电路传感器结构。 集成电路传感器结构包括包括电子电路的基板。 互连结构与衬底相邻。 互连结构包括通过互连结构的导电互连通孔。 电介质层与互连结构相邻。 电介质层包括平坦表面和穿过电介质层并电连接到互连通孔的导电电介质通孔。 电介质层还包括与互连结构相邻的层间平坦化介电层和与层间平坦化介电层相邻的钝化层。 集成电路传感器结构还包括与电介质层相邻的传感器。 互连通孔和电介质通孔将电子电路电连接到传感器。

公开(公告)号：US06265325B1

公开(公告)日：2001-07-24

申请号：US09299332

申请日：1999-04-26

申请人： Min Cao ,  Dietrich W Vook

发明人： Min Cao ,  Dietrich W Vook

IPC分类号： H01L2131

CPC分类号： H01L21/823462 ,  H01L21/3212

摘要： A method for fabricating dual gate dielectric layers on a semiconductor substrate involves utilizing a single photolithographic step to form layer stacks having two different gate dielectric layers and associated polysilicon layers, and then utilizing a physical planarization process to remove excess polysilicon and silicon oxide. According to the method, a first gate dielectric is formed on the first and second device areas of a substrate. A first polysilicon layer is deposited onto the first gate dielectric, and portions of the first polysilicon layer are removed utilizing a photolithographic process. The first gate dielectric is removed over the second device area, and a second, thinner gate dielectric is formed over the second device area. A second polysilicon layer is formed over the second gate dielectric and over the first polysilicon layer. The second polysilicon layer is then removed utilizing chemical mechanical polishing in order to form a common plane between the first polysilicon layer and the second polysilicon layer.

摘要翻译： 用于在半导体衬底上制造双栅介质层的方法包括利用单个光刻步骤来形成具有两个不同栅介电层和相关多晶硅层的层堆叠，然后利用物理平面化工艺去除多余的多晶硅和氧化硅。 根据该方法，在衬底的第一和第二器件区域上形成第一栅极电介质。 第一多晶硅层沉积到第一栅极电介质上，并且利用光刻工艺去除第一多晶硅层的部分。 在第二器件区域上去除第一栅极电介质，并且在第二器件区域上形成第二较薄的栅极电介质。 第二多晶硅层形成在第二栅极电介质上并在第一多晶硅层上方。 然后利用化学机械抛光去除第二多晶硅层，以在第一多晶硅层和第二多晶硅层之间形成公共平面。