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    Testing apparatus and method
    11.
    发明申请
    Testing apparatus and method 有权
    检测仪器及方法

    公开(公告)号：US20110128022A1

    公开(公告)日：2011-06-02

    申请号：US12798605

    申请日：2010-04-07

    申请人： Jae-Young Choi ,  Chang-Hyun Cho

    发明人： Jae-Young Choi ,  Chang-Hyun Cho

    IPC分类号： G01R31/02 ,  G01R31/26 ,  G01R31/3187

    CPC分类号： G01R31/318511

    摘要： A testing apparatus includes a test controller configured to output a plurality of chip selection signals for selecting chips to be tested from among a plurality of chips, a plurality of first control signals for controlling supply of a power supply voltage to the chips selected by the chip selection signals, and a plurality of second control signals for controlling receiving of test voltages output from the chips supplied with the power supply voltage, and a probe card including one or more test blocks each having a plurality of signal transmitters configured to respectively transfer the power supply voltage to the corresponding chips in response to the different first control signals and respectively apply the test voltages output from the corresponding chips to the test controller in response to the different second control signals.

    摘要翻译： 测试装置包括：测试控制器，被配置为从多个芯片中输出用于选择要测试的芯片的多个芯片选择信号;多个第一控制信号，用于控制向由芯片选择的芯片提供的电源电压 选择信号和多个第二控制信号，用于控制从提供有电源电压的芯片输出的测试电压的接收;以及探针卡，其包括一个或多个测试块，每个测试块具有多个信号发射机，其被配置为分别传输功率 响应于不同的第一控制信号向相应的芯片提供电压，并且响应于不同的第二控制信号分别将从相应芯片输出的测试电压施加到测试控制器。

    SEMICONDUCTOR MEMORY DEVICE INCLUDING STORAGE NODES AND RESISTORS AND METHOD OF MANFACTURING THE SAME
    12.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING STORAGE NODES AND RESISTORS AND METHOD OF MANFACTURING THE SAME 有权
    包含存储点和电阻的半导体存储器件及其制造方法

    公开(公告)号：US20060211192A1

    公开(公告)日：2006-09-21

    申请号：US11419710

    申请日：2006-05-22

    申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Yong-Seok Ahn

    发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Yong-Seok Ahn

    IPC分类号： H01L21/8244 ,  H01L21/8234

    CPC分类号： H01L27/10897 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10891 ,  H01L28/91

    摘要： A semiconductor memory device according to embodiments of the invention includes storage nodes and resistors. A method of manufacturing the semiconductor memory device according to some embodiments of the invention includes forming an interlayer insulation layer on a semiconductor substrate including a memory cell array area and a core/perimeter area; forming a first etch stop layer thereon; forming a plurality of contact plugs arranged linearly in at least one direction on the memory cell array area; forming a first conductive layer on the resultant structure; forming a second etch stop layer thereon; etching the second etch stop layer and the first conductive layer and forming landing pads and resistors arranged non-linearly in at least one direction; and forming storage nodes on the entire outer lateral surfaces of which are exposed, on the landing pads.

    摘要翻译： 根据本发明的实施例的半导体存储器件包括存储节点和电阻器。 根据本发明的一些实施例的制造半导体存储器件的方法包括在包括存储单元阵列区域和芯/周边区域的半导体衬底上形成层间绝缘层; 在其上形成第一蚀刻停止层; 形成在所述存储单元阵列区域上沿至少一个方向线性布置的多个接触插塞; 在所得结构上形成第一导电层; 在其上形成第二蚀刻停止层; 蚀刻所述第二蚀刻停止层和所述第一导电层并形成在至少一个方向上非线性地布置的着陆焊盘和电阻; 以及在其外侧表面的整个外表面上形成在着陆垫上露出的储存节点。

    Apparatus and method for testing a semiconductor device
    14.
    发明授权
    Apparatus and method for testing a semiconductor device 有权
    用于测试半导体器件的装置和方法

    公开(公告)号：US08525538B2

    公开(公告)日：2013-09-03

    申请号：US12710650

    申请日：2010-02-23

    申请人： Yanggi Kim ,  Chang-Hyun Cho ,  HoonJung Kim

    发明人： Yanggi Kim ,  Chang-Hyun Cho ,  HoonJung Kim

    IPC分类号： G01R31/00

    CPC分类号： G01R31/2887

    摘要： Provided are an apparatus and a method of testing a semiconductor device. A horizontal maintaining unit provided inside a test head applies load to a probe card in a direction perpendicular to the probe card to hold the probe card in a horizontal state.Probe needles of the probe card are uniformly placed on a central region of pads of the semiconductor device, thereby providing an apparatus and a method of testing a semiconductor device capable of improving productivity and reducing a yield loss of a test process.

    摘要翻译： 提供了一种测试半导体器件的装置和方法。 设置在测试头内部的水平保持单元沿垂直于探针卡的方向向探针卡施加负载，以将探针卡保持在水平状态。 探针卡的探头针均匀地放置在半导体器件的焊盘的中心区域上，从而提供能够提高生产率并降低测试过程的屈服损失的半导体器件的测试装置和方法。

    Method of forming self-aligned inner gate recess channel transistor
    15.
    发明申请
    Method of forming self-aligned inner gate recess channel transistor 有权
    形成自对准内门凹沟道晶体管的方法

    公开(公告)号：US20070096185A1

    公开(公告)日：2007-05-03

    申请号：US11641845

    申请日：2006-12-20

    申请人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

    发明人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

    IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119 ,  H01L21/8242

    CPC分类号： H01L21/28114 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7834

    摘要： A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.

    摘要翻译： 半导体衬底中的自对准内门凹槽通道包括形成在衬底的有源区中的凹槽，形成在凹槽的底部的栅介电层，形成在凹槽沟槽的侧壁上的凹陷内侧壁 形成在所述凹槽中的栅极，使得所述栅极的上部突出于所述基板的上表面之上，其中所述凹陷内侧壁间隔物的厚度使得所述栅极的中心部分具有比所述突出的上部 栅极的部分和下部，形成在栅极层上的栅极掩模，形成在栅极的突出上部上的栅极侧壁间隔物和栅极掩模，以及形成在邻近基板的基板的有源区域中的源极/漏极区域 门侧壁间隔件。

    Self-aligned inner gate recess channel transistor and method of forming the same
    16.
    发明授权
    Self-aligned inner gate recess channel transistor and method of forming the same 有权
    自对准内门凹槽通道晶体管及其形成方法

    公开(公告)号：US07154144B2

    公开(公告)日：2006-12-26

    申请号：US10730996

    申请日：2003-12-10

    申请人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

    发明人： Ji-Young Kim ,  Chang-Hyun Cho ,  Soo-Ho Shin ,  Tae-Young Chung

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/66553 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7834

    摘要： A self-aligned inner gate recess channel in a semiconductor substrate includes a recess trench formed in an active region of the substrate, a gate dielectric layer formed on a bottom portion of the recess trench, recess inner sidewall spacers formed on sidewalls of the recess trench, a gate formed in the recess trench so that an upper portion of the gate protrudes above an upper surface of the substrate, wherein a thickness of the recess inner sidewall spacers causes a center portion of the gate to have a smaller width than the protruding upper portion and a lower portion of the gate, a gate mask formed on the gate layer, gate sidewall spacers formed on the protruding upper portion of gate and the gate mask, and a source/drain region formed in the active region of the substrate adjacent the gate sidewall spacers.

    摘要翻译： 半导体衬底中的自对准内门凹槽通道包括形成在衬底的有源区中的凹槽，形成在凹槽的底部的栅介电层，形成在凹槽沟槽的侧壁上的凹陷内侧壁 形成在所述凹槽中的栅极，使得所述栅极的上部突出于所述基板的上表面之上，其中所述凹陷内侧壁间隔物的厚度使得所述栅极的中心部分具有比所述突出的上部 栅极的部分和下部，形成在栅极层上的栅极掩模，形成在栅极的突出上部上的栅极侧壁间隔物和栅极掩模，以及形成在邻近基板的基板的有源区域中的源极/漏极区域 门侧壁间隔件。

    Probe card for testing a plurality of semiconductor chips and method thereof
    17.
    发明申请
    Probe card for testing a plurality of semiconductor chips and method thereof 审中-公开
    用于测试多个半导体芯片的探针卡及其方法

    公开(公告)号：US20060170437A1

    公开(公告)日：2006-08-03

    申请号：US11330399

    申请日：2006-01-12

    申请人： Sang-Kyu Yoo ,  Ki-Sang Kang ,  Hoon-Jung Kim ,  Sung-Mo Kang ,  Chang-Hyun Cho

    发明人： Sang-Kyu Yoo ,  Ki-Sang Kang ,  Hoon-Jung Kim ,  Sung-Mo Kang ,  Chang-Hyun Cho

    IPC分类号： G01R31/02

    CPC分类号： G01R1/07364 ,  G01R1/0491

    摘要： A probe card for that may be used to test a plurality of semiconductor chips formed on a wafer. The probe card may include a substrate; a plurality of probe blocks that form a pattern corresponding to the pattern formed by the plurality of semiconductor chips formed on the wafer; and a plurality of probe needles formed in the probe blocks and arranged in a pattern corresponding to a plurality of pads formed in the plurality of semiconductor chips. The use of the probe card may decrease the testing time for the wafer.

    摘要翻译： 用于其的探针卡可用于测试形成在晶片上的多个半导体芯片。 探针卡可以包括基底; 多个探针块，其形成与由形成在晶片上的多个半导体芯片形成的图案对应的图案; 以及形成在探针块中的多个探针，并以与形成在多个半导体芯片中的多个焊盘相对应的图案布置。 探针卡的使用可能会降低晶片的测试时间。

    Devices with active areas having increased ion concentrations adjacent to isolation structures
    18.
    发明授权
    Devices with active areas having increased ion concentrations adjacent to isolation structures 失效
    具有活性区域的器件具有与隔离结构相邻的离子浓度增加

    公开(公告)号：US06768148B1

    公开(公告)日：2004-07-27

    申请号：US10403480

    申请日：2003-03-31

    申请人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

    发明人： Chang-Hyun Cho ,  Ki-Nam Kim ,  Sang-Hyeon Lee

    IPC分类号： H01L2976

    CPC分类号： H01L21/76237 ,  H01L21/823481

    摘要： Active areas of integrated circuits can be formed by implanting first ions into a first active area of a substrate adjacent to an isolation structure in the substrate and between a source and a drain region of the integrated circuit to provide a first concentration of ions in the first active area. Second ions are implanted into the first active area and a second active area of the substrate adjacent to the first active area and spaced-apart from the isolation structure on the substrate to provide a second concentration of ions in the second active area and a third concentration of ions in the first active area that is greater than the first and second concentrations. As a result, the level of ion concentration can be higher at the edge of an active channel region than at the center of the channel. The increased concentration of ions in the active area adjacent to the side wall of the trench may reduce a current between the source and drain regions of the transistor when voltage that is less than a threshold voltage of the transistor is applied to the gate electrode of the transistor. Thus, a reduction in the threshold voltage of the transistor can be inhibited. Integrated circuit transistors are also disclosed.

    摘要翻译： 可以通过将第一离子注入与衬底中的隔离结构相邻的衬底的第一有源区域中并且在集成电路的源极和漏极区域之间注入第一离子以形成第一离子的第一浓度来形成集成电路的有源区域 活动区域。 将第二离子注入与第一有源区相邻的第一有源区和衬底的第二有源区，并与衬底上的隔离结构间隔开，以在第二有源区中提供第二离子浓度，并且将第三浓度 的第一活性区域中的离子，其大于第一和第二浓度。 结果，在有源沟道区的边缘处，离子浓度的水平可高于通道中心处的离子浓度。 当沟槽的侧壁附近的有源区域中的离子浓度的增加可以减小晶体管的源极和漏极区域之间的电流，当小于晶体管的阈值电压的电压被施加到晶体管的栅电极时 晶体管。 因此，可以抑制晶体管的阈值电压的降低。 还公开了集成电路晶体管。

    Semiconductor memory device with built-in self test circuit
    19.
    发明授权
    Semiconductor memory device with built-in self test circuit 失效
    半导体存储器件内置自检电路

    公开(公告)号：US5946246A

    公开(公告)日：1999-08-31

    申请号：US996002

    申请日：1997-12-22

    申请人： Hong-Shin Jun ,  Chang-Hyun Cho

    发明人： Hong-Shin Jun ,  Chang-Hyun Cho

    IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/12 ,  G11C29/26 ,  G11C29/36 ,  G11C7/00

    CPC分类号： G11C29/36 ,  G11C29/26

    摘要： A semiconductor memory device with a built-in self test (BIST) circuit is disclosed including: a plurality of memory blocks; a plurality of selectors for selecting an address, a control signal and data of each memory block to a normal mode or a test mode in response to a BIST mode signal; a plurality of background generators for generating data to be written in each memory block and comparing data; a plurality of comparators for comparing data read from each memory block with the comparing data in response to the BIST mode signal and for generating a comparative result; a combination circuit for combining outputs of the plurality of comparator and for generating a test result; and a test controller for supplying a test address and a control signal to the plurality of selectors, for supplying a background number and an output inversion control signal to the plurality of background generators, and for supplying a comparing control signal to the plurality of comparators.

    摘要翻译： 公开了一种具有内置自检（BIST）电路的半导体存储器件，包括：多个存储器块; 多个选择器，用于响应于BIST模式信号，将地址，控制信号和每个存储块的数据选择为正常模式或测试模式; 多个后台生成器，用于生成要写入每个存储器块中的数据并比较数据; 多个比较器，用于将从每个存储器块读取的数据与响应于BIST模式信号的比较数据进行比较并产生比较结果; 用于组合多个比较器的输出并用于产生测试结果的组合电路; 以及用于向所述多个选择器提供测试地址和控制信号的测试控制器，用于向所述多个后台发生器提供背景号码和输出反相控制信号，以及用于向所述多个比较器提供比较控制信号。