公开(公告)号：US06543003B1

公开(公告)日：2003-04-01

申请号：US09436106

申请日：1999-11-08

申请人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  Larry Scott Leitner ,  Kevin Franklin Reick

发明人： Michael Stephen Floyd ,  James Allan Kahle ,  Hung Qui Le ,  Larry Scott Leitner ,  Kevin Franklin Reick

IPC分类号： G06F1100

CPC分类号： G06F9/3885 ,  G06F9/3861 ,  G06F11/0757 ,  G06F11/1405

摘要： A method and apparatus for recovering from a hang condition in a processor having a plurality of execution units. Monitoring is performed to detect a hang condition. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units are flushed.

摘要翻译： 一种用于在具有多个执行单元的处理器中从挂起状态恢复的方法和装置。 执行监视以检测挂起状况。 响应于检测挂起状况，分配给多个执行单元的指令被刷新。

公开(公告)号：US06654876B1

公开(公告)日：2003-11-25

申请号：US09434875

申请日：1999-11-04

申请人： Hung Qui Le ,  David James Shippy

发明人： Hung Qui Le ,  David James Shippy

IPC分类号： G06F930

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3865

摘要： A method, processor, and data processing system implementing a delayed reject mechanism are disclosed. The processor includes an issue unit suitable for issuing an instruction in a first cycle and a load store unit (LSU). The LSU includes an extend reject calculator circuit configured to receive a set of completion information signals and generate a delay value based thereon. The LSU is adapted to determine whether to reject the instruction in a determination cycle. The number of cycles between the first cycle and the determination cycle is a function of the delay value such that reject timing is variable with respect to the first cycle. In one embodiment, the processor is further configured to reissue the instruction after the determination cycle if the instruction was rejected in the determination cycle. The delay value is conveyed via a 2-bit bus in one embodiment. The 2 bit bus permits delaying the determination cycle from 0 to 3 cycles after a finish cycle. In one embodiment, the number of cycles between the first cycle and the determination cycle includes the number of cycles required to travel a pipeline of the microprocessor plus the number of cycles indicated by the delay value.

摘要翻译： 公开了一种实现延迟拒绝机制的方法，处理器和数据处理系统。 该处理器包括适于在第一周期中发出指令的发布单元和负载存储单元（LSU）。 LSU包括扩展拒绝计算器电路，被配置为接收一组完成信息信号并基于此生成延迟值。 LSU适于确定是否在确定周期中拒绝该指令。 第一周期和确定周期之间的周期数是延迟值的函数，使得拒绝定时相对于第一周期是可变的。 在一个实施例中，处理器还被配置为在确定周期之后重新发出指令，如果指令在确定周期中被拒绝。 在一个实施例中，延迟值通过2位总线传送。 2位总线允许在完成循环后将判定周期从0到3个周期延迟。 在一个实施例中，第一周期和确定周期之间的循环次数包括行进微处理器的流水线所需的循环次数加上由延迟值指示的周期数。

公开(公告)号：US08347068B2

公开(公告)日：2013-01-01

申请号：US11696363

申请日：2007-04-04

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Balaram Sinharoy

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3885

摘要： A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.

摘要翻译： 多模式寄存器重命名机制，允许同时多线程处理器在线程数量低时支持完全无序的线程执行，并且当线程数增加时按顺序执行线程。 响应于改变处理器的执行模式以按顺序执行线程执行模式，所述说明性实施例将数据处理系统中的物理寄存器切换到架构设施，从而形成切换的物理寄存器。 当向执行单元发出指令时，其中发出的指令包括一个线程位，检查该线程位以确定该指令是否访问一个架构设施。 如果发出的指令访问架构设施，则执行该指令，并且将所执行的指令的结果写入切换的物理寄存器。

公开(公告)号：US07904661B2

公开(公告)日：2011-03-08

申请号：US11953637

申请日：2007-12-10

申请人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

发明人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

摘要翻译： 在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。 数据预取请求被分配与数据流以反映确定的数据流的深度。 分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。 该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。 由处理器执行的指令中的预取控制位控制预取硬件配置。

公开(公告)号：US07827443B2

公开(公告)日：2010-11-02

申请号：US12270300

申请日：2008-11-13

申请人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

发明人： Susan Elizabeth Eisen ,  Hung Qui Le ,  Michael James Mack ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney

IPC分类号： G06F11/00

CPC分类号： G06F12/0888 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3863 ,  G06F11/1407

摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.

摘要翻译： 恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。 恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。 处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。 允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。 如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

公开(公告)号：US07650486B2

公开(公告)日：2010-01-19

申请号：US12013572

申请日：2008-01-14

申请人： Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto ,  Raymond Cheung Yeung

发明人： Hung Qui Le ,  Dung Quoc Nguyen ,  Brian William Thompto ,  Raymond Cheung Yeung

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/3836

摘要： A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instructions, from threads being processed simultaneously, to shared resources for which the multiple threads are competing. The existing resource vectors for instructions that are queued for issuance are analyzed and, where appropriate, dynamically recalculated and modified for maximum efficiency.

摘要翻译： 一种用于在问题时刻动态地转向指令的方法和装置，以便最大化由SMT处理器处理的多个线程共享的执行单元的使用效率。 在发布时使用资源向量将来自正在被处理的线程的指令重定向到多个线程正在竞争的共享资源。 分析用于发行排队的指令的现有资源向量，并在适当情况下动态重新计算和修改以最大限度地提高效率。

公开(公告)号：US07478276B2

公开(公告)日：2009-01-13

申请号：US11054988

申请日：2005-02-10

申请人： James Wilson Bishop ,  Hung Qui Le ,  Michael James Mack ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney ,  Brian William Thompto

发明人： James Wilson Bishop ,  Hung Qui Le ,  Michael James Mack ,  Jafar Nahidi ,  Dung Quoc Nguyen ,  Jose Angel Paredes ,  Scott Barnett Swaney ,  Brian William Thompto

IPC分类号： G06F11/00

CPC分类号： G06F11/1407

摘要： A method and apparatus are provided for dispatch group checkpointing in a microprocessor, including provisions for handling partially completed dispatch groups and instructions which modify system coherent state prior to completion. An instruction checkpoint retry mechanism is implemented to recover from soft errors in logic. The processor is able to dispatch fixed point unit (FXU), load/store unit (LSU), and floating point unit (FPU) or vector multimedia extension (VMX) instructions on the same cycle. Store data is written to a store queue when a store instruction finishes executing. The data is held in the store queue until the store instruction is checkpointed, at which point it can be released to the coherently shared level 2 (L2) cache.

摘要翻译： 提供了一种用于微处理器中的调度组检查点的方法和装置，包括用于处理部分完成的调度组的规定以及在完成之前修改系统相干状态的指令。 执行指令检查点重试机制以从逻辑中的软错误中恢复。 处理器能够在同一周期内调度固定点单元（FXU），加载/存储单元（LSU）和浮点单元（FPU）或矢量多媒体扩展（VMX）指令。 存储指令完成执行时，存储数据将写入存储队列。 数据保存在存储队列中，直到存储指令检查点为止，此时可将数据释放到相干共享的级别2（L2）缓存。

公开(公告)号：US07475223B2

公开(公告)日：2009-01-06

申请号：US11050367

申请日：2005-02-03

申请人： Brian R. Konigsburg ,  Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

发明人： Brian R. Konigsburg ,  Hung Qui Le ,  David Stephen Levitan ,  John Wesley Ward, III

IPC分类号： G06F9/00

CPC分类号： G06F9/3853 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/3851

摘要： An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping of instructions prior to the set of instructions being placed in the instruction cache.

摘要翻译： 用于分组指令的改进的方法，装置和计算机指令。 接收一组指令以放置在数据处理系统中的指令高速缓存中。 指令集中的指令在被放置在指令高速缓存中的指令集之前被分组成指令的分派组合。

公开(公告)号：US07421567B2

公开(公告)日：2008-09-02

申请号：US11016206

申请日：2004-12-17

申请人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

发明人： Richard James Eickemeyer ,  Hung Qui Le ,  Dung Quoc Nguyen ,  Benjamin Walter Stolt ,  Brian William Thompto

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3842 ,  G06F9/3804 ,  G06F9/383 ,  G06F9/3838

摘要： The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch. In speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available. Dependency and dirty (i.e. invalid result) bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions will then use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers will be used.

摘要翻译： 本发明允许微处理器在失速状态期间识别和推测地执行未来的指令。 这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。 这样的未来指令的执行可以启动来自远程高速缓存或主存储器的数据或指令的预取，或以其他方式通过指令流进行进展。 以这种方式，当在停止条件到期之后重新执行（不推测地执行）指令时，它们将以降低的执行延迟执行; 例如 通过访问预取到L1高速缓存中的数据，或者进入处理器，或通过在推测性地解决的误预测分支之后执行目标指令。 在推测模式中，由于缺少L1缓存的源加载，在推测执行模式下不可用的设备，或由于不可用的推测指令结果，指令操作数可能无效。 跟踪依赖关系和脏（即无效结果）位，并用于确定哪些推测指令对执行有效。 改进的值寄存器存储和位向量被用于提高推测结果的可用性，否则，由于不能将其写入到架构化的寄存器，否则将抛弃执行流水线。 修改后的通用寄存器用于在对应指令到达回写时存储推测结果，修改后的位向量跟踪存储在其中的结果。 当修改的位向量中的相应位指示数据已被修改时，不直接从旧指令旁路的较小的推测指令将使用该修改的数据。 否则，将使用来自架构化寄存器的数据。

公开(公告)号：US07302553B2

公开(公告)日：2007-11-27

申请号：US10351556

申请日：2003-01-23

申请人： Sam Gat-Shang Chu ,  Hung Qui Le ,  Dung Quoc Nguyen

发明人： Sam Gat-Shang Chu ,  Hung Qui Le ,  Dung Quoc Nguyen

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3836 ,  G06F9/3855 ,  G06F9/3857

摘要： An apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue of a processor are provided. Particularly, instructions are stored, one at a time at a clock cycle, in the non-moving queue. At every clock cycle, a present status of the instructions in the queue is recorded. Using the present status of the instructions in the queue in conjunction with previously recorded statuses of the instructions, the oldest instruction in the queue is determined. The status of the instructions in the queue includes whether or not the instruction has been issued for execution as well as whether or not it is known that the issued instruction has been accepted for execution.

摘要翻译： 提供了一种用于快速确定处理器的非移动指令队列中的最旧指令的装置，系统和方法。 特别地，在不移动队列中，以时钟周期一次存储指令。 在每个时钟周期，记录队列中的指令的当前状态。 结合队列中的指令的当前状态结合先前记录的指令状态，确定队列中最早的指令。 队列中的指令的状态包括是否已经发出指令执行，以及是否知道发出的指令已被接受执行。