公开(公告)号：US20060179206A1

公开(公告)日：2006-08-10

申请号：US11054066

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/06

CPC分类号： G06F13/1647 ,  G11C5/04 ,  Y02D10/14

摘要： A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the addresses of particular banks are folded into a single grouping. The banks are represented by the N copies of the bank control logic even when the total number of banks is greater than N. Each bank within the group is tagged as being busy when any one of the banks in the group is the target of a memory access request. The algorithm folds the addresses of the banks in an order that substantially minimizes the likelihood that a bank that is in a busy or false busy state will be the target of another memory access request. Power and logic savings are recognized as only N copies of bank control logic have to be supported.

公开(公告)号：US20060190685A1

公开(公告)日：2006-08-24

申请号：US11054182

申请日：2005-02-09

申请人： Richard Arndt ,  George Daly ,  James Fields ,  Warren Maule

发明人： Richard Arndt ,  George Daly ,  James Fields ,  Warren Maule

IPC分类号： G06F13/28 ,  G06F13/36

CPC分类号： G06F12/0837 ,  G06F12/084 ,  G06F12/1081 ,  G06F2212/1041 ,  G06F2212/683

摘要： A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.

摘要翻译： 公开了一种使翻译控制条目（TCE）高速缓存内的条目无效的方法和装置。 主机桥耦合在一组处理器和一组适配器之间。 主机桥包括TCE缓存。 TCE缓存包含位于系统内存中的TCE表中最近使用的TCE的副本。 响应于一个处理器对TCE表中的TCE进行修改，将存储器映射的输入/输出（MMIO）存储发送到TCE无效寄存器，以指定修改的TCE的地址。 然后使用TCE无效寄存器内的数据来产生用于使包含TCE表中修改的TCE的未修改副本的TCE缓存中的条目无效的命令。 该命令随后发送到主机桥，使TCE缓存中的条目无效。

公开(公告)号：US20060179334A1

公开(公告)日：2006-08-10

申请号：US11054392

申请日：2005-02-09

申请人： Mark Brittain ,  Edgar Cordero ,  James Fields ,  Warren Maule ,  Eric Retter

发明人： Mark Brittain ,  Edgar Cordero ,  James Fields ,  Warren Maule ,  Eric Retter

IPC分类号： G06F1/32

CPC分类号： G06F1/3225 ,  G06F1/206 ,  Y02D10/16

摘要： A method and system for enabling directed temperature/power management at the DIMM-level and/or DRAM-level utilizing intelligent scheduling of memory access operations received at the memory controller. Hot spots within the memory subsystem, caused by operating the DIMMs/DRAMs above predetermined/preset threshold power/temperature values for operating a DIMM and/or a DRAM, are avoided/controlled by logic within the memory controller. The memory controller logic throttles the number/frequency at which commands (read/write operations) are issued to the specific DIMM/DRAM based on feedback data received from the specific DIMM/DRAM reaching the preset threshold power usage value.

摘要翻译： 一种用于利用在存储器控制器处接收的存储器访问操作的智能调度在DIMM级和/或DRAM级实现定向温度/电源管理的方法和系统。 由存储器控制器内的逻辑避免/控制存储器子系统内由于将DIMM / DRAM操作在用于操作DIMM和/或DRAM的预定/预设阈值功率/温度值以上的热点。 存储器控制器逻辑基于从特定DIMM / DRAM接收的反馈数据达到预设阈值功率使用值，来限制向特定DIMM / DRAM发出命令（读/写操作）的数量/频率。

公开(公告)号：US20080046796A1

公开(公告)日：2008-02-21

申请号：US11851527

申请日：2007-09-07

申请人： Timothy Dell ,  Kevin Gower ,  Warren Maule

发明人： Timothy Dell ,  Kevin Gower ,  Warren Maule

IPC分类号： H03M13/00

CPC分类号： G11C5/04

摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

摘要翻译： 具有存储器总线和存储器组件的存储器子系统。 存储器总线包括多个位线。 存储器组件与存储器总线通信，并且包括用于经由存储器总线接收多个分组中的错误代码校正（ECC）字的指令。 ECC字包括排列成多个多位ECC符号的数据位和ECC位。 每个ECC符号与存储器总线上的位线之一相关联。 存储器组件还包括用于利用ECC符号之一对经由与ECC符号相关联的位层接收的ECC字中的比特进行错误检测和校正的指令。

公开(公告)号：US20070183331A1

公开(公告)日：2007-08-09

申请号：US11736196

申请日：2007-04-17

申请人： Paul Coteus ,  Kevin Gower ,  Warren Maule ,  Robert Tremaine

发明人： Paul Coteus ,  Kevin Gower ,  Warren Maule ,  Robert Tremaine

IPC分类号： H04J1/16

CPC分类号： G06F13/1657 ,  G06F13/1673

摘要： A method and system for providing indeterminate read data latency in a memory system. The method includes determining if a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The method also includes determining if the buffer device contains a data packet and determining if an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The method further includes determining if an upstream data packet has been received. The upstream data packet is in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver.

摘要翻译： 一种用于在存储器系统中提供不确定的读取数据等待时间的方法和系统。 该方法包括确定是否已经接收到本地数据分组。 如果接收到本地数据分组，则本地数据分组被存储到缓冲设备中。 该方法还包括确定缓冲器装置是否包含数据包，并确定是否经由上游信道将数据包发送到存储器控制器的上行驱动器空闲。 如果缓冲区包含数据包，并且上游驱动程序处于空闲状态，则将数据包传送到上游驱动程序。 该方法还包括确定是否已经接收到上游数据分组。 上行数据包是帧格式，包括帧开始指示符和存储器控制器在将上行数据包与其对应的读取指令相关联时使用的识别标签。 如果已经接收到上游数据分组，并且上游驱动程序不空闲，则上游数据分组被存储到缓冲设备中。 如果已经接收到上游数据分组，并且缓冲设备不包含数据分组，并且上游驱动器空闲，则将上游数据分组发送到上游驱动程序。 如果上游驱动程序不空闲，那么正在进行的任何数据分组都将继续传输到上游驱动程序。

公开(公告)号：US20060179333A1

公开(公告)日：2006-08-10

申请号：US11054374

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule

发明人： Mark Brittain ,  Warren Maule

IPC分类号： G11C5/00

CPC分类号： G11C11/4096 ,  G11C5/143 ,  G11C7/04 ,  G11C11/4074

摘要： A method and system for enabling directed temperature/power management at the DIMM-level and/or DRAM-level utilizing intelligent scheduling of memory access operations received at the memory controller. Hot spots within the memory subsystem, caused by operating the DIMMs/DRAMs above predetermined/preset threshold power/temperature values for operating a DIMM and/or a DRAM, are avoided/controlled by logic within the memory controller. The memory controller logic throttles the number/frequency at which commands (read/write operations) are issued to the specific DIMM/DRAM based on stored parameter values and tracking of outstanding operations issued to the memory subsystem devices.

摘要翻译： 一种用于利用在存储器控制器处接收的存储器访问操作的智能调度在DIMM级和/或DRAM级实现定向温度/电源管理的方法和系统。 由存储器控制器内的逻辑避免/控制存储器子系统内由于将DIMM / DRAM操作在高于用于操作DIMM和/或DRAM的预定阈值功率/温度值以上的DIMM / DRAM的热点。 存储器控制器逻辑基于存储的参数值和发出到存储器子系统设备的未完成操作的跟踪，来控制向特定DIMM / DRAM发出命令（读/写操作）的数量/频率。

公开(公告)号：US20060095671A1

公开(公告)日：2006-05-04

申请号：US10977846

申请日：2004-10-29

申请人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

发明人： Kevin Gower ,  Mark Kellogg ,  Warren Maule ,  Thomas Smith ,  Robert Tremaine

IPC分类号： G06F13/00

CPC分类号： G06F13/1684 ,  G06F12/0802 ,  G06F2212/401

摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

公开(公告)号：US20070300129A1

公开(公告)日：2007-12-27

申请号：US11851485

申请日：2007-09-07

申请人： Timothy Dell ,  Kevin Gower ,  Warren Maule

发明人： Timothy Dell ,  Kevin Gower ,  Warren Maule

IPC分类号： G11C29/52

CPC分类号： G11C5/04

摘要： A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data bits and ECC bits arranged into multiple multi-bit ECC symbols. Each of the ECC symbols is associated with one of the bitlanes on the memory bus. The memory assembly also includes instructions for utilizing one of the ECC symbols to perform error detection and correction for the bits in the ECC word received via the bitlane associated with the ECC symbol.

摘要翻译： 具有存储器总线和存储器组件的存储器子系统。 存储器总线包括多个位线。 存储器组件与存储器总线通信，并且包括用于经由存储器总线接收多个分组中的错误代码校正（ECC）字的指令。 ECC字包括排列成多个多位ECC符号的数据位和ECC位。 每个ECC符号与存储器总线上的位线之一相关联。 存储器组件还包括用于利用ECC符号之一对经由与ECC符号相关联的位层接收的ECC字中的比特进行错误检测和校正的指令。

公开(公告)号：US20060095646A1

公开(公告)日：2006-05-04

申请号：US10977793

申请日：2004-10-29

申请人： Kevin Gower ,  Warren Maule

发明人： Kevin Gower ,  Warren Maule

IPC分类号： G06F12/14

CPC分类号： G06F13/1684

摘要： A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.

摘要翻译： 一种用于实现存储器子系统命令接口的系统，该系统包括包括一个或多个存储器模块，存储器控制器和存储器总线的级联互连系统。 存储器控制器生成包括多个命令的数据帧。 存储器控制器和存储器模块通过存储器总线通过分组化的多传输接口互连，并且帧经由存储器总线传送到存储器模块。

公开(公告)号：US4254879A

公开(公告)日：1981-03-10

申请号：US932230

申请日：1978-08-09

申请人： Warren Maule

发明人： Warren Maule

IPC分类号： A47F7/024 ,  G11B33/04 ,  A47F7/00

CPC分类号： G11B33/045 ,  A47F7/024 ,  Y10T70/5009

摘要： A unique phonograph record holder is provided with locking means to prevent the unauthorized removal of phonogrph records from the holder. The record holder comprises an elongated support which is maintained in a vertical and elevated position by either a stand or by securing the support to a wall. A first and second elongated rod extend perpendicularly outwardly from the support so that the rods are horizontal and in a spaced and parallel relationship. Phonograph records having a central aperture are then positioned over one of the elongated rods so that the rod extends through the record aperture. A locking link is detachably secured across the free ends of the rods to prevent the unauthorized removal of phonograph records from the holder.

摘要翻译： 独特的留声机记录保持器配有锁定装置，以防止持卡人未经授权地移除声音记录。 记录保持器包括细长的支撑件，其通过支架或通过将支撑件固定到墙壁而保持在垂直和升高的位置。 第一和第二细长杆从支撑件垂直向外延伸，使得杆是水平的并且以间隔和平行的关系。 然后将具有中心孔的留声机记录物定位在一根细长杆上，使得杆延伸穿过记录孔。 锁定连接件可以可拆卸地固定在杆的自由端上，以防止未经授权从保持器中移除留声机记录。