公开(公告)号：US20060121662A1

公开(公告)日：2006-06-08

申请号：US10904884

申请日：2004-12-02

申请人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

发明人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US20080096370A1

公开(公告)日：2008-04-24

申请号：US11955436

申请日：2007-12-13

申请人： Brent Anderson ,  John Ellis-Monaghan ,  Alain Loiseau ,  Kirk Peterson

发明人： Brent Anderson ,  John Ellis-Monaghan ,  Alain Loiseau ,  Kirk Peterson

IPC分类号： H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/8252

摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.

摘要翻译： 公开了制造双取向晶片的方法。 在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。 沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。 形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。 另外的隔离结构形成在沟槽内和半导体层内的硅材料内。 对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。 所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。

公开(公告)号：US20070235780A1

公开(公告)日：2007-10-11

申请号：US11765485

申请日：2007-06-20

申请人： John Ellis-Monaghan ,  Mark Jaffe ,  Alain Loiseau

发明人： John Ellis-Monaghan ,  Mark Jaffe ,  Alain Loiseau

IPC分类号： H01L31/0352

CPC分类号： H01L27/14643 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14679

摘要： An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.

摘要翻译： 成像电路，成像传感器和成像方法。 所述成像单元电路包括一个或多个成像单元电路，每个成像单元电路包括：晶体管，具有浮动体，用于响应于浮体暴露于电磁辐射而保持在浮体中产生的电荷; 用于偏置晶体管的装置，其中晶体管的输出响应于电磁辐射; 以及用于选择性地将浮动体连接到复位电压源的装置。

公开(公告)号：US20070187734A1

公开(公告)日：2007-08-16

申请号：US11276085

申请日：2006-02-14

申请人： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Dale Pearson ,  Dennis Rogers

发明人： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Dale Pearson ,  Dennis Rogers

IPC分类号： H01L31/062

CPC分类号： H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

摘要翻译： 一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。 感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离， 基材表面。 在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于形成在基底表面处的掺杂层的下方。

公开(公告)号：US20070013072A1

公开(公告)日：2007-01-18

申请号：US11160468

申请日：2005-06-24

申请人： John Ellis-Monaghan ,  Jeffrey Gambino ,  Timothy Sullivan ,  Steven Voldman

发明人： John Ellis-Monaghan ,  Jeffrey Gambino ,  Timothy Sullivan ,  Steven Voldman

IPC分类号： H01L23/52

CPC分类号： H01L27/0248 ,  Y10S438/926

摘要： A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.

摘要翻译： 一种用于在集成电路制造期间耗散电荷的方法，结构和设计方法。 该结构包括：衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

公开(公告)号：US20060226456A1

公开(公告)日：2006-10-12

申请号：US10907570

申请日：2005-04-06

申请人： James Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Jerome Lasky ,  Richard Phelps

发明人： James Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Jeffrey Gambino ,  Mark Jaffe ,  Jerome Lasky ,  Richard Phelps

IPC分类号： H01L31/113

CPC分类号： H01L27/14689 ,  H01L27/14603 ,  H01L27/14609 ,  H01L31/0352

摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.

摘要翻译： 像素传感器单元结构及其制造方法。 像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。 减少了由钉扎层引起的对电荷转移的电势障碍干扰。

公开(公告)号：US20060163670A1

公开(公告)日：2006-07-27

申请号：US10905945

申请日：2005-01-27

申请人： John Ellis-Monaghan ,  Dale Martin ,  William Murphy ,  James Nakos ,  Kirk Peterson

发明人： John Ellis-Monaghan ,  Dale Martin ,  William Murphy ,  James Nakos ,  Kirk Peterson

IPC分类号： H01L29/76

CPC分类号： H01L29/7845 ,  H01L21/28052 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconducting structure and a method of forming thereof, includes a substrate having a p-type device region and an n-type device region; a first-type suicide contact to the n-type device region; the first-type suicide having a work function that is substantially aligned to the n-type device region conduction band; and a second-type silicide contact to the p-type device region; the second-type silicide having a work function that is substantially aligned to the p-type device region valence band. The present invention also provides a semiconducting structure and a method of forming therefore, in which the silicide contact material and silicide contact processing conditions are selected to provide strain based device improvements in pFET and nFET devices.

摘要翻译： 半导体结构及其形成方法包括具有p型器件区域和n型器件区域的衬底; 与n型器件区域的第一类型的硅化物接触; 具有基本上与n型器件区域导带对准的功函数的第一型硅化物; 和与p型器件区域的第二类型硅化物接触; 所述第二类型硅化物具有基本上对准所述p型器件区域价带的功函数。 本发明还提供了半导体结构及其形成方法，其中选择硅化物接触材料和硅化物接触处理条件以在pFET和nFET器件中提供基于应变的器件改进。

公开(公告)号：US20060118835A1

公开(公告)日：2006-06-08

申请号：US10904896

申请日：2004-12-03

申请人： John Ellis-Monaghan ,  Jeffrey Johnson ,  Alain Loiseau

发明人： John Ellis-Monaghan ,  Jeffrey Johnson ,  Alain Loiseau

IPC分类号： H01L31/062

CPC分类号： H01L27/14601 ,  H01L27/14612 ,  H01L27/14689

摘要： A novel Active Pixel Sensor (APS) cell structure and method of manufacture. Particularly, an image sensor APS cell having a predoped transfer gate is formed that avoids the variations of Vt as a result of subsequent manufacturing steps. According to the preferred embodiment of the invention, the image sensor APS cell structure includes a doped p-type pinning layer and an n-type doped gate. There is additionally provided a method of forming the image sensor APS cell having a predoped transfer gate and a doped pinning layer. The predoped transfer gate prevents part of the gate from becoming p-type doped.

摘要翻译： 一种新型的有源像素传感器（APS）单元结构及其制造方法。 特别地，形成具有预定传输门的图像传感器APS单元，其避免了作为后续制造步骤的结果的V变化。 根据本发明的优选实施例，图像传感器APS单元结构包括掺杂的p型钉扎层和n型掺杂栅极。 还提供了一种形成具有预制传输栅极和掺杂钉扎层的图像传感器APS单元的方法。 预制传输门防止栅极的一部分变成p型掺杂。

公开(公告)号：US20060102939A1

公开(公告)日：2006-05-18

申请号：US11276085

申请日：2006-02-14

申请人： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Dale Pearson ,  Dennis Rogers

发明人： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Dale Pearson ,  Dennis Rogers

IPC分类号： H01L31/062

摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

公开(公告)号：US20130260183A1

公开(公告)日：2013-10-03

申请号：US13432353

申请日：2012-03-28

申请人： John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed Hickory Rankin

发明人： John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed Hickory Rankin

IPC分类号： H01M2/00 ,  G06F19/00

CPC分类号： H01M10/425 ,  H01M2/22 ,  H01M2/26 ,  H01M4/0473 ,  H01M4/386 ,  H01M10/0525 ,  H01M10/0562 ,  H01M10/058 ,  H01M2220/30 ,  H01M2300/0068 ,  Y10T29/49108

摘要： A solid-state battery structure having a plurality of battery cells formed in a substrate. The plurality of battery cells includes a first current collector layer overlying a first insulating layer and a first electrode layer overlying the first current collector layer. The battery structure further includes a second current collector layer overlying a patterned second electrode layer. The patterned second electrode layer overlies the substrate and forms a plurality of sub-arrays of the battery cells. The battery structure further includes a second insulating layer overlying the second current collector layer. The second insulating layer substantially laterally surrounds first and second contact pads. The first pad is electrically connected to the first current collector layer and the second pad is electrically connected to the second current collector layer. The first and second contact pads are in electrical communication, through at least two electrical wires, with a circuit located upon the substrate.

摘要翻译： 一种具有形成在基板中的多个电池单元的固态电池结构。 多个电池单元包括覆盖第一绝缘层的第一集电器层和覆盖第一集电器层的第一电极层。 电池结构还包括覆盖图案化的第二电极层的第二集电器层。 图案化的第二电极层覆盖在衬底上并形成电池单元的多个子阵列。 电池结构还包括覆盖第二集电器层的第二绝缘层。 第二绝缘层基本上横向围绕第一和第二接触焊盘。 第一焊盘电连接到第一集电器层，第二焊盘电连接到第二集电器层。 第一和第二接触焊盘通过至少两根电线电连接，电路位于衬底上。