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    THREE DIMENSIONAL SOLID-STATE BATTERY INTEGRATED WITH CMOS DEVICES
    1.
    发明申请
    THREE DIMENSIONAL SOLID-STATE BATTERY INTEGRATED WITH CMOS DEVICES 审中-公开
    三维固态电池与CMOS器件集成

    公开(公告)号：US20130260183A1

    公开(公告)日：2013-10-03

    申请号：US13432353

    申请日：2012-03-28

    申请人： John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed Hickory Rankin

    发明人： John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed Hickory Rankin

    IPC分类号： H01M2/00 ,  G06F19/00

    CPC分类号： H01M10/425 ,  H01M2/22 ,  H01M2/26 ,  H01M4/0473 ,  H01M4/386 ,  H01M10/0525 ,  H01M10/0562 ,  H01M10/058 ,  H01M2220/30 ,  H01M2300/0068 ,  Y10T29/49108

    摘要： A solid-state battery structure having a plurality of battery cells formed in a substrate. The plurality of battery cells includes a first current collector layer overlying a first insulating layer and a first electrode layer overlying the first current collector layer. The battery structure further includes a second current collector layer overlying a patterned second electrode layer. The patterned second electrode layer overlies the substrate and forms a plurality of sub-arrays of the battery cells. The battery structure further includes a second insulating layer overlying the second current collector layer. The second insulating layer substantially laterally surrounds first and second contact pads. The first pad is electrically connected to the first current collector layer and the second pad is electrically connected to the second current collector layer. The first and second contact pads are in electrical communication, through at least two electrical wires, with a circuit located upon the substrate.

    摘要翻译： 一种具有形成在基板中的多个电池单元的固态电池结构。 多个电池单元包括覆盖第一绝缘层的第一集电器层和覆盖第一集电器层的第一电极层。 电池结构还包括覆盖图案化的第二电极层的第二集电器层。 图案化的第二电极层覆盖在衬底上并形成电池单元的多个子阵列。 电池结构还包括覆盖第二集电器层的第二绝缘层。 第二绝缘层基本上横向围绕第一和第二接触焊盘。 第一焊盘电连接到第一集电器层，第二焊盘电连接到第二集电器层。 第一和第二接触焊盘通过至少两根电线电连接，电路位于衬底上。

    PIXEL SENSOR CELL INCLUDING LIGHT SHIELD
    2.
    发明申请
    PIXEL SENSOR CELL INCLUDING LIGHT SHIELD 有权
    像素传感器细胞，包括光泽

    公开(公告)号：US20100230729A1

    公开(公告)日：2010-09-16

    申请号：US12538194

    申请日：2009-08-10

    申请人： John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

    发明人： John Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Richard J. Rassel

    IPC分类号： H01L27/148 ,  H01L27/146 ,  H01L31/0216 ,  H01L21/30 ,  G06F17/50

    CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/1464

    摘要： CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate

    摘要翻译： CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背面照明的光屏蔽 像素传感器单元。 在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽 遮光层。 在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器代替浮动扩散，并且被定位在载体衬底上的电介质隔离金属化堆叠中

    Pixel sensor cell including light shield
    3.
    发明授权
    Pixel sensor cell including light shield 有权
    像素传感器单元包括遮光罩

    公开(公告)号：US09543356B2

    公开(公告)日：2017-01-10

    申请号：US12538194

    申请日：2009-08-10

    申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  John Ellis-Monaghan ,  Richard Rassel

    发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  John Ellis-Monaghan ,  Richard Rassel

    IPC分类号： H01L27/148 ,  H01L27/146

    CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/1464

    摘要： CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.

    摘要翻译： CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背侧照明的光屏蔽 像素传感器单元。 在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽 遮光层。 在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器来代替浮动扩散，并且被定位在载体衬底上的介电隔离金属化堆叠中。

    3-DIMENSIONAL INTEGRATED CIRCUIT TESTING USING MEMS SWITCHES WITH TUNGSTEN CONE CONTACTS
    6.
    发明申请
    3-DIMENSIONAL INTEGRATED CIRCUIT TESTING USING MEMS SWITCHES WITH TUNGSTEN CONE CONTACTS 有权
    采用微机电开关的三维集成电路测试

    公开(公告)号：US20130200910A1

    公开(公告)日：2013-08-08

    申请号：US13364345

    申请日：2012-02-02

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    IPC分类号： G01R1/067 ,  H01L21/768

    CPC分类号： G01R1/06727 ,  B81B2203/0118 ,  B81C1/00111 ,  G01R1/06738 ,  G01R1/06744 ,  G01R1/07342 ,  G01R3/00 ,  H01L21/76804 ,  H01L21/76885 ,  H01L22/14 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).

    摘要翻译： 一种用于测试多层三维集成电路（IC）的测试系统，其中临时连接两个独立的IC电路层以实现功能性，包括具有三维IC的第一部分的被测芯片，以及 测试探针芯片，其具有第三部分的IC和微机电系统（MEMS）开关，其选择性地完成第一IC层中的第三部分的第三部分之间的功能电路和第二部分内的电路 的三维IC在第二IC层中。 MEMS开关包括钨（W）锥形触点，其使得被测芯片的电路和测试探针芯片之间的选择性电接触，并且使用梯度硼磷硅酸盐玻璃（BPSG）的模板形成。

    Nitride etch for improved spacer uniformity
    7.
    发明授权
    Nitride etch for improved spacer uniformity 失效
    氮化物蚀刻用于改善间隔物均匀性

    公开(公告)号：US08470713B2

    公开(公告)日：2013-06-25

    申请号：US12966432

    申请日：2010-12-13

    申请人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Christa R. Willets

    发明人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin ,  Christa R. Willets

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31116 ,  H01L21/28035 ,  H01L21/76237 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/78

    摘要： A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.

    摘要翻译： 一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。 在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。 在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。 所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。

    Method and structure to prevent circuit network charging during fabrication of integrated circuits
    8.
    发明授权
    Method and structure to prevent circuit network charging during fabrication of integrated circuits 失效
    在集成电路制造过程中防止电路网络充电的方法和结构

    公开(公告)号：US08120141B2

    公开(公告)日：2012-02-21

    申请号：US11687711

    申请日：2007-03-19

    申请人： Jeffrey P. Gambino ,  Kirk D. Peterson

    发明人： Jeffrey P. Gambino ,  Kirk D. Peterson

    IPC分类号： H01L21/00 ,  H01L21/82

    CPC分类号： H01L27/1203 ,  H01L23/5256 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.

    摘要翻译： 集成电路及其制造方法。 该集成电路包括：一个或多个配电网络; 一个或多个地面分配网络; 一个或多个数据网络; 并且将相同或不同网络的电力，地线或数据线临时并电连接在一起，从由一个或多个配电网络，一个或多个配电网络，一个或多个配电网络组成的组中选择的相同或不同的网络， 更多数据网络及其组合。

    Variable Focus Point Lens
    9.
    发明申请
    Variable Focus Point Lens 有权
    可变焦点镜头

    公开(公告)号：US20110208482A1

    公开(公告)日：2011-08-25

    申请号：US12708561

    申请日：2010-02-19

    申请人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    发明人： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    IPC分类号： G06F17/50 ,  G02B3/12

    CPC分类号： G02B3/14

    摘要： A variable focal point lens includes a transparent tank, which comprises a transparent enclosure containing a transparent flexible membrane separating the inner volume of the transparent tank into an upper tank portion and a lower tank portion. The upper tank portion and the lower tank portion contain liquids having different indices of refraction. The transparent flexible membrane is electrostatically displaced to change the thicknesses of the first tank portion and the second tank portion in the path of the light, thereby shifting the focal point of the lens axially and/or laterally. The electrostatic displacement of the membrane may be effected by a fixed charge in the membrane and an array of enclosure-side conductive structures on the transparent enclosure, or an array of membrane-side conductive structures on the transparent membrane and an array of enclosure-side conductive structures.

    摘要翻译： 可变焦点透镜包括透明容器，透明容器包括透明的外壳，该透明外壳包含将透明容器的内部容积分隔成上部容器部分和下部容器部分的透明柔性膜。 上罐部分和下罐部分含有不同折射率的液体。 透明柔性膜被静电移位以改变光路中的第一罐部分和第二罐部分的厚度，从而轴向和/或横向地移动透镜的焦点。 膜的静电位移可以通过膜中的固定电荷和透明外壳上的封闭侧导电结构阵列，或透明膜上的膜侧导电结构阵列和外壳侧阵列 导电结构。

    SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS
    10.
    发明申请
    SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS 有权
    用于校正集成电路芯片的系统参数变化的系统和方法，以最小化电路有限的损失

    公开(公告)号：US20110098838A1

    公开(公告)日：2011-04-28

    申请号：US12603679

    申请日：2009-10-22

    申请人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    发明人： James A. Culp ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/10

    摘要： Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.

    摘要翻译： 公开了一种用于校正集成电路芯片上的系统的，基于设计的参数变化的系统和方法，以最小化电路限制的产量损失。 存储处理信息和芯片的映射。 处理信息可以指示给定设备参数对与给定过程步骤相关联的规范的值的变化的影响。 地图可以指示设备参数中的区域变化（例如，阈值电压）。 基于处理信息并使用该图作为指导，确定规范的不同值，每个值在处理步骤期间应用于集成电路芯片的不同区域，以便抵消映射的区域参数变化。 然后可以选择性地控制处理工具，以确保在芯片制造期间相应地执行工艺步骤，从而确保区域参数变化最小化。