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公开(公告)号:US20240332427A1
公开(公告)日:2024-10-03
申请号:US18604840
申请日:2024-03-14
Applicant: Japan Display Inc.
Inventor: Marina MOCHIZUKI , Masahiro WATABE , Masashi TSUBUKU , Hajime WATAKABE , Toshinari SASAKI , Takaya TAMARU , Ryo ONODERA
IPC: H01L29/786 , H01L29/417 , H01L29/66
CPC classification number: H01L29/7869 , H01L29/41733 , H01L29/6675
Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, a metal oxide layer over the gate insulating layer, an oxide semiconductor layer having a polycrystalline structure over the metal oxide layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode, wherein the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer, and a difference between a thickness of the first region and a thickness of the second region is 5 nm or less.
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公开(公告)号:US20240312999A1
公开(公告)日:2024-09-19
申请号:US18588249
申请日:2024-02-27
Applicant: Japan Display Inc.
Inventor: Hajime WATAKABE , Masashi TSUBUKU , Toshinari SASAKI , Takaya TAMARU , Marina MOCHIZUKI , Ryo ONODERA
IPC: H01L27/12
CPC classification number: H01L27/1225 , H01L27/1251
Abstract: A semiconductor device includes a first transistor on a substrate and a second transistor on the first transistor. The first transistor includes a first gate electrode on the substrate, a first insulating film on the first gate electrode, a first oxide semiconductor layer on the first insulating film, having a region overlapping the first gate electrode, and having a polycrystalline structure, a second insulating film on the first oxide semiconductor layer, and a second gate electrode on the second insulating film. The second transistor includes a third gate electrode on the second insulating film, a third insulating film on the third gate electrode, a second oxide semiconductor layer on the third insulating film and having a region overlapping the third gate electrode, a fourth insulating film on the second oxide semiconductor layer, and a fourth gate electrode on the fourth insulating film.
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公开(公告)号:US20240178325A1
公开(公告)日:2024-05-30
申请号:US18519392
申请日:2023-11-27
Applicant: Japan Display Inc.
Inventor: Hajime WATAKABE , Masashi TSUBUKU , Toshinari SASAKI , Takaya TAMARU , Marina MOCHIZUKI , Ryo ONODERA
IPC: H01L29/786 , H01L29/06
CPC classification number: H01L29/7869 , H01L29/0603 , H01L29/78696
Abstract: A semiconductor device includes an oxide insulating layer, an oxide semiconductor layer on the oxide insulating layer, a gate insulating layer on and in contact with the oxide semiconductor layer, and a gate electrode on the gate insulating layer. The oxide semiconductor layer includes a channel region overlapping the gate electrode, and source and drain regions that do not overlap the gate electrode. At an interface between the source and drain regions and the gate insulating layer, a concentration of an impurity on a surface of at least one of the source and drain regions is greater than or equal to 1×1019 cm−3.
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公开(公告)号:US20210257402A1
公开(公告)日:2021-08-19
申请号:US17167081
申请日:2021-02-04
Applicant: Japan Display Inc.
Inventor: Hajime WATAKABE , Akihiro HANADA , Marina MOCHIZUKI , Ryo ONODERA , Fumiya KIMURA , Isao SUZUMURA
IPC: H01L27/146
Abstract: The present invention provides a technology which realizes a reliable semiconductor device including a photosensor device by preventing pent roofs of edges of a P+ layer from being generated and a metal wiring installed over the P+ layer from coming down while securing the electrical conductivity of the P+ layer. The semiconductor device includes a photosensor including a photodiode formed on a substrate. The photodiode includes: a cathode electrode; a laminated structure that is formed on the cathode electrode and in which an N+ layer, an I layer, and a P+ layer are laminated in this order; an anode electrode formed on the P+ layer; a first insulating film formed so as to cover a portion of the anode electrode and edges of the laminated structure; and a metal wiring connected to the anode electrode. The edges of the laminated structure are formed in forward tapered shapes in a cross-sectional view.
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公开(公告)号:US20250113625A1
公开(公告)日:2025-04-03
申请号:US18897125
申请日:2024-09-26
Applicant: Japan Display Inc.
Inventor: Hajime WATAKABE , Masashi TSUBUKU , Toshinari SASAKI , Takaya TAMARU , Marina MOCHIZUKI , Masahiro WATABE
IPC: H01L31/119 , H01L25/04 , H01L31/02 , H01L31/0224
Abstract: A radiation detector according to an embodiment of the present invention includes: a transistor in which an oxide semiconductor layer is used in a channel of the transistor; a photoelectric converting layer connected to the transistor; a wavelength converting layer facing the photoelectric converting layer and capable of emitting visible light based on radioactive rays absorbed by the wavelength converting layer; and an oxide layer in contact with the oxide semiconductor layer between the transistor and the photoelectric converting layer, wherein a thickness of the oxide layer is 50 nm or less.
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公开(公告)号:US20240332429A1
公开(公告)日:2024-10-03
申请号:US18618022
申请日:2024-03-27
Applicant: Japan Display Inc.
Inventor: Masahiro WATABE , Hajime WATAKABE , Masashi TSUBUKU , Toshinari SASAKI , Marina MOCHIZUKI , Takaya TAMARU , Ryo ONODERA
IPC: H01L29/786 , H01L27/12 , H01L29/66
CPC classification number: H01L29/7869 , H01L27/1225 , H01L29/66742 , H01L29/78696
Abstract: A semiconductor device comprises a metal oxide layer on an insulating surface; an oxide semiconductor layer on the metal oxide layer; a gate insulating layer on the oxide semiconductor layer; and a gate wiring on the gate insulating layer. The metal oxide layer has a first region overlapping the gate wiring and the oxide semiconductor layer, a second region overlapping the oxide semiconductor layer and not overlapping the gate wiring, and a third region overlapping the gate wiring and not overlapping the oxide semiconductor layer.
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公开(公告)号:US20240332308A1
公开(公告)日:2024-10-03
申请号:US18597186
申请日:2024-03-06
Applicant: Japan Display Inc.
Inventor: Marina MOCHIZUKI , Masahiro WATABE , Masashi TSUBUKU , Hajime WATAKABE , Toshinari SASAKI , Takaya TAMARU , Ryo ONODERA
IPC: H01L27/12 , G02F1/1368 , H01L29/786 , H10K59/121
CPC classification number: H01L27/1225 , G02F1/1368 , H01L27/1274 , H01L29/7869 , H10K59/1213
Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer having a polycrystalline structure over the gate insulating layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer. The interlayer insulating layer covers the source electrode and the drain electrode. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer. A difference between a film thickness of the first region and a film thickness of the second region is less than or equal to 5 nm.
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公开(公告)号:US20240250091A1
公开(公告)日:2024-07-25
申请号:US18411028
申请日:2024-01-12
Applicant: Japan Display Inc.
Inventor: Masahiro WATABE , Hajime WATAKABE , Masashi TSUBUKU , Toshinari SASAKI , Marina MOCHIZUKI , Takaya TAMARU , Ryo ONODERA
IPC: H01L27/12 , G02F1/1368 , H01L29/786
CPC classification number: H01L27/124 , H01L27/1225 , H01L29/7869 , G02F1/1368
Abstract: A semiconductor device includes an oxide semiconductor layer including a polycrystalline structure, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer connected to the oxide semiconductor layer, and a second transparent conductive layer arranged in the same layer as the first transparent conductive layer and separated from the first transparent conductive layer, wherein crystallizability of the first transparent conductive layer is different from crystallizability of the second transparent conductive layer.
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公开(公告)号:US20240215381A1
公开(公告)日:2024-06-27
申请号:US18395906
申请日:2023-12-26
Applicant: Japan Display Inc.
Inventor: Hayata AOKI , Jun NITTA , Marina MOCHIZUKI
IPC: H10K59/80 , H10K59/122
CPC classification number: H10K59/80517 , H10K59/122 , H10K59/80523 , H10K59/80524 , H10K59/873
Abstract: According to one embodiment, a display device includes a plurality of pixels and a bank provided between each adjacent pair of the plurality of pixels, and each of the plurality of pixels includes, on a base, a cathode, an organic EL layer provided on the cathode, a protective layer provided to cover a side surface of the organic EL layer, and an anode provided on the protective layer and in an aperture of the bank, so as to be in contact with the organic EL layer.
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公开(公告)号:US20220077344A1
公开(公告)日:2022-03-10
申请号:US17527192
申请日:2021-11-16
Applicant: Japan Display Inc.
Inventor: Masashi TSUBUKU , Takanori TSUNASHIMA , Marina MOCHIZUKI
IPC: H01L31/12 , H01L31/101 , G06F1/16
Abstract: A photo sensor circuit includes: a photo transistor; a first switching transistor; a second switching transistor; and a capacitance element. The photo transistor includes: a gate connected to a first wiring; a source connected to a second wiring; and a drain. The first switching transistor includes: a gate connected to a third wiring; a source connected to a fourth wiring; and a drain connected to the drain of the photo transistor. The capacitance element includes: a first terminal connected to the drain of the photo transistor; and a second terminal connected to the source of the first switching transistor. The second switching transistor includes: a gate connected to a gate line; a source connected to a signal line; and a drain connected to the first terminal of the capacitance element. The photo transistor, first switching transistor, and second transistor each include an oxide semiconductor layer as a channel layer.
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