公开(公告)号：US06194309B1

公开(公告)日：2001-02-27

申请号：US09366552

申请日：1999-08-04

申请人： Gyo-Young Jin

发明人： Gyo-Young Jin

IPC分类号： H01L21425

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a contact of a semiconductor device is described, in which a conductive layer pattern is electrically connected to a semiconductor substrate and an interlayer insulating film is formed on the semiconductor substrate including the conductive layer pattern. The interlayer insulating film is etched down to a top surface of the conductive layer pattern using a contact formation mask to form a contact hole. The conductive layer pattern is isotropically etched through the contact hole so as to extend the surface area of the exposed conductive layer pattern and the contact hole is filled with conductive material, forming a contact plug electrically connected to the conductive layer pattern. It is therefore possible to extend the contact area between the conductive layer pattern and a contact plug. As a result, the contact resistance is reduced.

摘要翻译： 描述了一种用于形成半导体器件的接触的方法，其中导电层图案电连接到半导体衬底，并且在包括导电层图案的半导体衬底上形成层间绝缘膜。 使用接触形成掩模将层间绝缘膜蚀刻到导电层图案的顶表面以形成接触孔。 通过接触孔对导电层图案进行各向同性蚀刻，以便延长暴露的导电层图案的表面积，并且用导电材料填充接触孔，形成电连接到导电层图案的接触插塞。 因此可以延长导电层图案和接触插塞之间的接触面积。 结果，接触电阻降低。

公开(公告)号：US07833864B2

公开(公告)日：2010-11-16

申请号：US11738620

申请日：2007-04-23

申请人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

发明人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

IPC分类号： H01L21/8234

CPC分类号： H01L21/823878 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/518

摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

摘要翻译： 实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。 一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。 此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极 地区。 实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

公开(公告)号：US07622778B2

公开(公告)日：2009-11-24

申请号：US11383141

申请日：2006-05-12

申请人： Sung-Sam Lee ,  Gyo-Young Jin ,  Yun-Gi Kim

发明人： Sung-Sam Lee ,  Gyo-Young Jin ,  Yun-Gi Kim

IPC分类号： H01L23/62

CPC分类号： H01L21/76232

摘要： In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.

摘要翻译： 在一个实施例中，半导体器件具有由形成在STI沟槽内部的隔离层限定的有源区，该隔离层包括上沟槽和下沟槽，所述上沟槽和下沟槽在所述上沟槽下方具有基本弯曲的横截面轮廓，使得所述下沟槽处于连通状态 与上沟槽。 由于上沟槽具有以正斜率渐缩的侧壁，因此当用绝缘层填充上沟槽时，可以获得良好的间隙填充性能。 通过在下沟槽中形成空隙，隔离层底部的介电常数低于氧化物层的介电常数，从而提高隔离性能。 隔离层包括仅在上沟槽内形成的第一绝缘层，并且以间隔物的形式覆盖上沟槽的内壁。

公开(公告)号：US07307008B2

公开(公告)日：2007-12-11

申请号：US10622915

申请日：2003-07-18

申请人： Yong-Chul Oh ,  Gyo-Young Jin

发明人： Yong-Chul Oh ,  Gyo-Young Jin

IPC分类号： H01L21/425

CPC分类号： H01L21/76897 ,  H01L21/76895

摘要： Methods of forming a cell pad contact hole on an integrated circuit include forming adjacent gates on an integrated circuit substrate having a source/drain region extending between the gates. Gate spacers are formed on facing sidewalls of the adjacent gates. A cell pad contact hole is formed aligned to the gates and gate spacers that exposes the source/drain region in the integrated circuit substrate. A first poly film is formed in the cell pad contact hole. An ion region is formed in the source/drain region by ion-implanting through the first poly film and a second poly film is formed on the first poly film that substantially fills the cell pad contact hole.

摘要翻译： 在集成电路上形成单元焊盘接触孔的方法包括在集成电路基板上形成相邻栅极，该集成电路基板具有在栅极之间延伸的源极/漏极区域。 栅极间隔物形成在相邻栅极的相对侧壁上。 形成与栅极和栅极间隔物对准的电池垫接触孔，其暴露集成电路基板中的源极/漏极区域。 在电池垫接触孔中形成第一多晶膜。 通过离子注入第一多晶硅膜，在源极/漏极区域中形成离子区，而在第一多晶膜上形成基本上填充电池垫接触孔的第二多晶硅膜。

公开(公告)号：US20050153490A1

公开(公告)日：2005-07-14

申请号：US11014212

申请日：2004-12-15

申请人： Jae-Man Yoon ,  Gyo-Young Jin ,  Hee-Soo Kang ,  Dong-Gun Park

发明人： Jae-Man Yoon ,  Gyo-Young Jin ,  Hee-Soo Kang ,  Dong-Gun Park

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78609

摘要： According to some embodiments, a fin type active region is formed under an exposure state of sidewalls on a semiconductor substrate. A gate insulation layer is formed on an upper part of the active region and on the sidewalls, and a device isolation film surrounds the active region to an upper height of the active region. The sidewalls are partially exposed by an opening part formed on the device isolation film. The opening part is filled with a conductive layer that partially covers the upper part of the active region, forming a gate electrode. Source and drain regions are on a portion of the active region where the gate electrode is not. The gate electrode may be easily separated and problems causable by etch by-product can be substantially reduced, and a leakage current of channel region and an electric field concentration onto an edge portion can be prevented.

摘要翻译： 根据一些实施例，在半导体衬底上的侧壁的曝光状态下形成鳍型有源区。 在有源区的上部和侧壁上形成栅极绝缘层，并且器件隔离膜将活性区域包围到有源区的上部高度。 侧壁由形成在器件隔离膜上的开口部分部分露出。 开口部分填充有部分覆盖有源区的上部的导电层，形成栅电极。 源极和漏极区域在栅电极不是的有源区域的一部分上。 可以容易地分离栅极电极，并且可以显着地减少由蚀刻副产物引起的问题，并且可以防止沟道区域的漏电流和电场集中在边缘部分上。

公开(公告)号：US20050048729A1

公开(公告)日：2005-03-03

申请号：US10898484

申请日：2004-07-22

申请人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

发明人： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

IPC分类号： H01L21/334 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66545 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/66537

摘要： A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

摘要翻译： 根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区， 并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。 该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成 栅极区域中的第三杂质区域。 该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。