公开(公告)号：US08609538B2

公开(公告)日：2013-12-17

申请号：US13764398

申请日：2013-02-11

申请人： Darrell G. Hill ,  Bruce M. Green

发明人： Darrell G. Hill ,  Bruce M. Green

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An electronic device having a conductive substrate via extending between a conductor on a rear face and a conductor over a front face of the substrate includes a multi-layered etch-stop beneath the front surface conductor. The etch-stop permits use of a single etchant to penetrate both the substrate and any overlying semiconductor and/or dielectric without attacking the overlying front surface conductor. This is especially important when the semiconductor and dielectric are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop is preferably a stack of N≧2 pairs of sub-layers, where a first sub-layer comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer comprises etch resistant material (e.g., Ni). In a further embodiment, where the device includes field effect transistors having feedback sensitive control gates, the etch-stop material is advantageously used to form gate shields.

摘要翻译： 具有通过在后表面上的导体与衬底的前表面之间的导体之间延伸的导电衬底的电子器件包括在前表面导体下方的多层蚀刻停止。 蚀刻停止允许使用单个蚀刻剂来穿透基板和任何上覆的半导体和/或电介质，而不会攻击上覆的前表面导体。 当半导体和电介质如此薄以至于在蚀刻期间达到这些区域时阻止改变蚀刻剂时，这尤其重要。 蚀刻停止优选地是N> = 2对子层的堆叠，其中第一子层包括减轻应力和/或粘附促进材料（例如，Ti），并且第二子层包括耐蚀刻材料 （例如Ni）。 在另一实施例中，其中器件包括具有反馈敏感控制栅极的场效应晶体管，蚀刻停止材料有利地用于形成栅极屏蔽。

公开(公告)号：US08946779B2

公开(公告)日：2015-02-03

申请号：US13777858

申请日：2013-02-26

申请人： Bruce M. Green ,  James A. Teplik

发明人： Bruce M. Green ,  James A. Teplik

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/812 ,  H01L29/80 ,  H01L29/20

CPC分类号： H01L27/0629 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/51 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7839 ,  H01L29/812

摘要： A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.

摘要翻译： 半导体器件包括：衬底，其包括异质结构，该异质结构被配置为在操作期间支持通道的形成，由衬底支撑的第一和第二电介质层，第二介电层设置在第一介电层和衬底之间，栅极由衬底支撑 ，设置在所述第一介电层中的第一开口中，并且在操作期间施加偏置电压以控制通过所述沟道的电流，所述第二介电层设置在所述栅极和所述衬底之间，以及由所述衬底支撑的电极 ，设置在第一和第二电介质层中的第二开口中，并且被配置为与衬底建立肖特基结。

公开(公告)号：US08592878B2

公开(公告)日：2013-11-26

申请号：US13042948

申请日：2011-03-08

申请人： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

发明人： Bruce M. Green ,  Haldane S. Henry ,  Chun-Li Liu ,  Karen E. Moore ,  Matthias Passlack

IPC分类号： H01L29/66

CPC分类号： H01L21/28581 ,  H01L21/28587 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/475 ,  H01L29/7787

摘要： Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.

摘要翻译： 实施例包括具有低泄漏肖特基接触的半导体器件。 通过提供部分完成的半导体器件形成一个实施例，该半导体器件包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。 在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除第一掩模。 使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。 通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。

公开(公告)号：US20130157456A1

公开(公告)日：2013-06-20

申请号：US13764398

申请日：2013-02-11

申请人： Darrell G. Hill ,  Bruce M. Green

发明人： Darrell G. Hill ,  Bruce M. Green

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An electronic device having a conductive substrate via extending between a conductor on a rear face and a conductor over a front face of the substrate includes a multi-layered etch-stop beneath the front surface conductor. The etch-stop permits use of a single etchant to penetrate both the substrate and any overlying semiconductor and/or dielectric without attacking the overlying front surface conductor. This is especially important when the semiconductor and dielectric are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop is preferably a stack of N≧2 pairs of sub-layers, where a first sub-layer comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer comprises etch resistant material (e.g., Ni). In a further embodiment, where the device includes field effect transistors having feedback sensitive control gates, the etch-stop material is advantageously used to form gate shields.

摘要翻译： 具有通过在后表面上的导体与衬底的前表面之间的导体之间延伸的导电衬底的电子器件包括在前表面导体下方的多层蚀刻停止。 蚀刻停止允许使用单个蚀刻剂来穿透基板和任何上覆的半导体和/或电介质，而不会攻击上覆的前表面导体。 当半导体和电介质如此薄以至于在蚀刻期间达到这些区域时阻止改变蚀刻剂时，这尤其重要。 蚀刻停止优选地是N> = 2对子层的堆叠，其中第一子层包括减轻应力和/或粘附促进材料（例如，Ti），并且第二子层包括耐蚀刻材料 （例如Ni）。 在另一实施例中，其中器件包括具有反馈敏感控制栅极的场效应晶体管，蚀刻停止材料有利地用于形成栅极屏蔽。

公开(公告)号：US08193591B2

公开(公告)日：2012-06-05

申请号：US11404714

申请日：2006-04-13

申请人： Bruce M. Green ,  Haldane S. Henry

发明人： Bruce M. Green ,  Haldane S. Henry

IPC分类号： H01L21/00

CPC分类号： H01L29/0657 ,  G03F9/7073 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L29/2003 ,  H01L29/812 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Semiconductor devices (61) and methods (80-89, 100) are provided with dual passivation layers (56, 59). A semiconductor layer (34) is formed on a substrate (32) and covered by a first passivation layer (PL-1) (56). PL-1 (56) and part (341) of the semiconductor layer (34) are etched to form a device mesa (35). A second passivation layer (PL-2) (59) is formed over PL-1 (56) and exposed edges (44) of the mesa (35). Vias (90, 92, 93) are etched through PL-1 (56) and PL-2 (59) to the semiconductor layer (34) where source (40), drain (42) and gate are to be formed. Conductors (41, 43, 39) are applied in the vias (90, 92, 93) for ohmic contacts for the source-drain (40, 42) and a Schottky contact (39) for the gate. Interconnections (45, 47) over the edges (44) of the mesa (35) couple other circuit elements. PL-1 (56) avoids adverse surface states (52) near the gate and PL-2 (59) insulates edges (44) of the mesa (35) from overlying interconnections (45, 47) to avoid leakage currents (46). An opaque alignment mark (68) is desirably formed at the same time as the device (61) to facilitate alignment when using transparent semiconductors (34).

摘要翻译： 半导体器件（61）和方法（80-89,100）具有双重钝化层（56,59）。 半导体层（34）形成在基板（32）上并被第一钝化层（PL-1）（56）覆盖。 半导体层（34）的PL-1（56）和部分（341）被蚀刻以形成器件台面（35）。 在台面（35）的PL-1（56）和暴露边缘（44）上形成第二钝化层（PL-2）（59）。 通孔（90,92,93）通过PL-1（56）和PL-2（59）蚀刻到要形成源极（40），漏极（42）和栅极的半导体层（34）。 导体（41,43,39）被施加在通孔（90,92,93）中，用于源极漏极（40,42）的欧姆接触和用于栅极的肖特基接触（39）。 台面（35）的边缘（44）之间的互连（45,47）耦合其他电路元件。 PL-1（56）避免栅极附近的不利表面状态（52），并且PL-2（59）使台面（35）的边缘（44）与上覆互连（45,47）绝缘，以避免泄漏电流（46）。 在使用透明半导体（34）时，期望与器件（61）同时形成不透明对准标记（68）以便于对准。

公开(公告)号：US06867078B1

公开(公告)日：2005-03-15

申请号：US10716955

申请日：2003-11-19

申请人： Bruce M. Green ,  Olin L. Hartin ,  Lawrence S. Klingbeil ,  Ellen Y. Lan ,  Hsin-Hua P. Li ,  Charles E. Weitzel

发明人： Bruce M. Green ,  Olin L. Hartin ,  Lawrence S. Klingbeil ,  Ellen Y. Lan ,  Hsin-Hua P. Li ,  Charles E. Weitzel

IPC分类号： H01L21/335 ,  H01L29/423 ,  H01L29/778 ,  H01L21/338 ,  H01L21/3205

CPC分类号： H01L29/66462 ,  H01L29/42316 ,  H01L29/7785

摘要： A microwave field effect transistor (10) has a high conductivity gate (44) overlying a double heterojunction structure (14, 18, 22) that has an undoped channel layer (18). The heterojunction structure overlies a substrate (12). A recess layer that is a not intentionally doped (NID) layer (24) overlies the heterojunction structure and is formed with a predetermined thickness that minimizes impact ionization effects at an interface of a drain contact of source/drain ohmic contacts (30) and permits significantly higher voltage operation than previous step gate transistors. Another recess layer (26) is used to define a gate dimension. A Schottky gate opening (42) is formed within a step gate opening (40) to create a step gate structure. A channel layer (18) material of InxGa1−xAs is used to provide a region of electron confinement with improved transport characteristics that result in higher frequency of operation, higher power density and improved power-added efficiency.

摘要翻译： 微波场效应晶体管（10）具有覆盖具有未掺杂沟道层（18）的双异质结结构（14,18,22）的高导电性栅极（44）。 异质结结构覆盖在基板（12）上。 作为非有意掺杂（NID）层（24）的凹陷层覆盖在异质结结构上并形成预定的厚度，使得在源极/漏极欧姆接触（30）的漏极接触的界面处的冲击电离效应最小化并允许 比上一级栅晶体管显着更高的电压操作。 另一个凹陷层（26）用于限定门尺寸。 肖特基门开口（42）形成在步进门开口（40）内以形成阶梯门结构。 使用In x Ga 1-x As的沟道层（18）材料来提供具有改善的传输特性的电子约束区域，这导致更高的操作频率，更高的功率密度和更好的功率附加效率。

公开(公告)号：US09362198B2

公开(公告)日：2016-06-07

申请号：US14249538

申请日：2014-04-10

申请人： Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L M Mahalingam

发明人： Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L M Mahalingam

IPC分类号： H01L31/102 ,  H01L23/367 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/04 ,  H01L21/28 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

CPC分类号： H01L23/373 ,  H01L21/042 ,  H01L21/0475 ,  H01L21/28 ,  H01L21/32051 ,  H01L21/762 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/04026 ,  H01L2224/29026 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

摘要翻译： 半导体器件的实施例包括半导体衬底，其包括主体衬底和上表面，有源区域，半导体衬底中的由凹陷表面局部限定的衬底开口，以及设置在半导体衬底上的导热层 其在有源区域内在凹入表面和半导体衬底的一部分之间延伸。 制造半导体器件的方法包括限定有源区域，在有源区域中的沟道上形成栅电极，在栅电极的相对侧上的有源区域中形成源电极和漏电极，蚀刻栅电极的衬底开口 所述半导体衬底由所述凹陷表面部分地限定，并且在所述半导体衬底上沉积导热层，所述导热层在所述沟道上在所述凹陷表面和所述半导体衬底的一部分之间延伸。

公开(公告)号：US20150123168A1

公开(公告)日：2015-05-07

申请号：US14594286

申请日：2015-01-12

申请人： Bruce M. Green ,  James A. Teplik

发明人： Bruce M. Green ,  James A. Teplik

IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L27/0629 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/51 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7839 ,  H01L29/812

摘要： A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.

摘要翻译： 半导体器件包括：衬底，其包括异质结构，该异质结构被配置为在操作期间支持通道的形成，由衬底支撑的第一和第二电介质层，第二介电层设置在第一介电层和衬底之间，栅极由衬底支撑 ，设置在所述第一介电层中的第一开口中，并且在操作期间施加偏置电压以控制通过所述沟道的电流，所述第二介电层设置在所述栅极和所述衬底之间，以及由所述衬底支撑的电极 ，设置在第一和第二电介质层中的第二开口中，并且被配置为与衬底建立肖特基结。

公开(公告)号：US20140061659A1

公开(公告)日：2014-03-06

申请号：US13603801

申请日：2012-09-05

申请人： James A. Teplik ,  Bruce M. Green

发明人： James A. Teplik ,  Bruce M. Green

IPC分类号： H01L29/78 ,  H01L21/335

CPC分类号： H01L29/402 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7789

摘要： A low leakage current transistor (2) is provided which includes a GaN-containing substrate (11-14) covered by a passivation surface layer (17) in which a T-gate electrode with sidewall extensions (20) is formed and coated with a multi-level passivation layer (30-32) which includes an intermediate etch stop layer (31) which is used to define a continuous multi-region field plate (33) having multiple distances between the bottom surface of the field plate 33 and the semiconductor substrate in the gate-drain region of the transistor.

摘要翻译： 提供了一种低漏电流晶体管（2），其包括由钝化表面层（17）覆盖的含GaN衬底（11-14），其中形成具有侧壁延伸部（20）的T形栅电极，并涂覆有 多级钝化层（30-32），其包括中间蚀刻停止层（31），其用于限定在场板33的底表面和半导体器件的半导体层之间具有多个距离的连续多区域场板（33） 衬底在晶体管的栅极 - 漏极区域中。

公开(公告)号：US20120175777A1

公开(公告)日：2012-07-12

申请号：US13005240

申请日：2011-01-12

申请人： Darrell G. Hill ,  Bruce M. Green

发明人： Darrell G. Hill ,  Bruce M. Green

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An electronic device (50) having a conductive substrate via (70) extending between a conductor (39) on a rear face (22) and a conductor (58) over the front surface (23) of the substrate (21) includes a multi-layered etch-stop (56, 56-2) beneath the front surface conductor (58). The etch-stop (56, 56-2) permits use of a single etchant to penetrate both the substrate (21) and any overlying semiconductor (44) and/or dielectric (34) without attacking the overlying front surface conductor (58). This is especially important when the semiconductor (44) and dielectric (34) are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop (56) is preferably a stack (63, 73) of N≧2 pairs (62-i) of sub-layers (62-i1, 62-i2) in either order, where a first sub-layer (62-i1) comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer (62-i2) comprises etch resistant material (e.g., Ni). In a further embodiment, where the device (50) includes field effect transistors (52) having feedback sensitive control gates (30), the etch-stop material (56) is advantageously used to form gate shields (76).

摘要翻译： 具有在背面（22）上的导体（39）与衬底（21）的前表面（23）之间的导体（58）之间延伸的导电衬底通孔（70）的电子器件（50）包括多 在前表面导体（58）下面的层间蚀刻停止（56,56-2）。 蚀刻停止（56,56-2）允许使用单个蚀刻剂来穿透基板（21）和任何上覆的半导体（44）和/或电介质（34），而不会攻击上覆的前表面导体（58）。 当半导体（44）和电介质（34）如此薄以至于在蚀刻期间达到这些区域时阻止改变蚀刻剂时，这尤其重要。 蚀刻停止（56）优选地是以任何顺序的N≥2对（62-i）子层（62-i1,62-i2）的堆叠（63,73），其中第一子层 62-i1）包括应力释放和/或粘附促进材料（例如Ti），并且第二子层（62-i2）包括耐蚀刻材料（例如Ni）。 在另一实施例中，在器件（50）包括具有反馈敏感控制栅极（30）的场效应晶体管（52）的情况下，蚀刻停止材料（56）有利地用于形成栅极屏蔽（76）。