公开(公告)号：US09362198B2

公开(公告)日：2016-06-07

申请号：US14249538

申请日：2014-04-10

申请人： Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L M Mahalingam

发明人： Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L M Mahalingam

IPC分类号： H01L31/102 ,  H01L23/367 ,  H01L21/762 ,  H01L21/3205 ,  H01L21/04 ,  H01L21/28 ,  H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

CPC分类号： H01L23/373 ,  H01L21/042 ,  H01L21/0475 ,  H01L21/28 ,  H01L21/32051 ,  H01L21/762 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/04026 ,  H01L2224/29026 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

摘要翻译： 半导体器件的实施例包括半导体衬底，其包括主体衬底和上表面，有源区域，半导体衬底中的由凹陷表面局部限定的衬底开口，以及设置在半导体衬底上的导热层 其在有源区域内在凹入表面和半导体衬底的一部分之间延伸。 制造半导体器件的方法包括限定有源区域，在有源区域中的沟道上形成栅电极，在栅电极的相对侧上的有源区域中形成源电极和漏电极，蚀刻栅电极的衬底开口 所述半导体衬底由所述凹陷表面部分地限定，并且在所述半导体衬底上沉积导热层，所述导热层在所述沟道上在所述凹陷表面和所述半导体衬底的一部分之间延伸。

公开(公告)号：US20150294921A1

公开(公告)日：2015-10-15

申请号：US14249538

申请日：2014-04-10

申请人： LAKSHMINARAYAN VISWANATHAN ,  Bruce M. Green ,  Darrell G. Hill ,  L. M. Mahalingam

发明人： LAKSHMINARAYAN VISWANATHAN ,  Bruce M. Green ,  Darrell G. Hill ,  L. M. Mahalingam

IPC分类号： H01L23/367 ,  H01L21/762 ,  H01L29/778 ,  H01L21/04 ,  H01L21/28 ,  H01L29/06 ,  H01L21/3205

CPC分类号： H01L23/373 ,  H01L21/042 ,  H01L21/0475 ,  H01L21/28 ,  H01L21/32051 ,  H01L21/762 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/04026 ,  H01L2224/29026 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

摘要翻译： 半导体器件的实施例包括半导体衬底，其包括主体衬底和上表面，有源区域，半导体衬底中的由凹陷表面局部限定的衬底开口，以及设置在半导体衬底上的导热层 其在有源区域内在凹入表面和半导体衬底的一部分之间延伸。 制造半导体器件的方法包括限定有源区域，在有源区域中的沟道上形成栅电极，在栅电极的相对侧上的有源区域中形成源电极和漏电极，蚀刻栅电极的衬底开口 所述半导体衬底由所述凹陷表面部分地限定，并且在所述半导体衬底上沉积导热层，所述导热层在所述沟道上在所述凹陷表面和所述半导体衬底的一部分之间延伸。

公开(公告)号：US08946776B2

公开(公告)日：2015-02-03

申请号：US13533610

申请日：2012-06-26

申请人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC分类号： H01L29/812

CPC分类号： H01L21/28581 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

摘要翻译： 半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及 第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。 图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。

公开(公告)号：US08609538B2

公开(公告)日：2013-12-17

申请号：US13764398

申请日：2013-02-11

申请人： Darrell G. Hill ,  Bruce M. Green

发明人： Darrell G. Hill ,  Bruce M. Green

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An electronic device having a conductive substrate via extending between a conductor on a rear face and a conductor over a front face of the substrate includes a multi-layered etch-stop beneath the front surface conductor. The etch-stop permits use of a single etchant to penetrate both the substrate and any overlying semiconductor and/or dielectric without attacking the overlying front surface conductor. This is especially important when the semiconductor and dielectric are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop is preferably a stack of N≧2 pairs of sub-layers, where a first sub-layer comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer comprises etch resistant material (e.g., Ni). In a further embodiment, where the device includes field effect transistors having feedback sensitive control gates, the etch-stop material is advantageously used to form gate shields.

摘要翻译： 具有通过在后表面上的导体与衬底的前表面之间的导体之间延伸的导电衬底的电子器件包括在前表面导体下方的多层蚀刻停止。 蚀刻停止允许使用单个蚀刻剂来穿透基板和任何上覆的半导体和/或电介质，而不会攻击上覆的前表面导体。 当半导体和电介质如此薄以至于在蚀刻期间达到这些区域时阻止改变蚀刻剂时，这尤其重要。 蚀刻停止优选地是N> = 2对子层的堆叠，其中第一子层包括减轻应力和/或粘附促进材料（例如，Ti），并且第二子层包括耐蚀刻材料 （例如Ni）。 在另一实施例中，其中器件包括具有反馈敏感控制栅极的场效应晶体管，蚀刻停止材料有利地用于形成栅极屏蔽。

公开(公告)号：US09685345B2

公开(公告)日：2017-06-20

申请号：US14084335

申请日：2013-11-19

申请人： Bruce M. Green ,  Darrell G. Hill ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Karen E. Moore

IPC分类号： H01L29/15 ,  H01L21/311 ,  H01L29/872 ,  H01L29/66 ,  H01L23/544 ,  H01L29/47 ,  H01L29/778 ,  H01L27/06 ,  H01L27/095 ,  H01L21/027 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/0272 ,  H01L21/31111 ,  H01L23/544 ,  H01L27/0605 ,  H01L27/095 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66143 ,  H01L29/66431 ,  H01L29/812 ,  H01L29/872 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.

公开(公告)号：US09153448B2

公开(公告)日：2015-10-06

申请号：US14601804

申请日：2015-01-21

申请人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC分类号： H01L21/285 ,  H01L21/311 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  H01L29/10 ,  H01L29/812 ,  H01L29/20

CPC分类号： H01L21/28581 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

公开(公告)号：US20130341678A1

公开(公告)日：2013-12-26

申请号：US13533610

申请日：2012-06-26

申请人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC分类号： H01L29/812 ,  H01L29/778 ,  H01L21/311

CPC分类号： H01L21/28581 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

摘要翻译： 半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及 第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。 图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。

公开(公告)号：US20120175777A1

公开(公告)日：2012-07-12

申请号：US13005240

申请日：2011-01-12

申请人： Darrell G. Hill ,  Bruce M. Green

发明人： Darrell G. Hill ,  Bruce M. Green

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An electronic device (50) having a conductive substrate via (70) extending between a conductor (39) on a rear face (22) and a conductor (58) over the front surface (23) of the substrate (21) includes a multi-layered etch-stop (56, 56-2) beneath the front surface conductor (58). The etch-stop (56, 56-2) permits use of a single etchant to penetrate both the substrate (21) and any overlying semiconductor (44) and/or dielectric (34) without attacking the overlying front surface conductor (58). This is especially important when the semiconductor (44) and dielectric (34) are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop (56) is preferably a stack (63, 73) of N≧2 pairs (62-i) of sub-layers (62-i1, 62-i2) in either order, where a first sub-layer (62-i1) comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer (62-i2) comprises etch resistant material (e.g., Ni). In a further embodiment, where the device (50) includes field effect transistors (52) having feedback sensitive control gates (30), the etch-stop material (56) is advantageously used to form gate shields (76).

摘要翻译： 具有在背面（22）上的导体（39）与衬底（21）的前表面（23）之间的导体（58）之间延伸的导电衬底通孔（70）的电子器件（50）包括多 在前表面导体（58）下面的层间蚀刻停止（56,56-2）。 蚀刻停止（56,56-2）允许使用单个蚀刻剂来穿透基板（21）和任何上覆的半导体（44）和/或电介质（34），而不会攻击上覆的前表面导体（58）。 当半导体（44）和电介质（34）如此薄以至于在蚀刻期间达到这些区域时阻止改变蚀刻剂时，这尤其重要。 蚀刻停止（56）优选地是以任何顺序的N≥2对（62-i）子层（62-i1,62-i2）的堆叠（63,73），其中第一子层 62-i1）包括应力释放和/或粘附促进材料（例如Ti），并且第二子层（62-i2）包括耐蚀刻材料（例如Ni）。 在另一实施例中，在器件（50）包括具有反馈敏感控制栅极（30）的场效应晶体管（52）的情况下，蚀刻停止材料（56）有利地用于形成栅极屏蔽（76）。

公开(公告)号：US20150132932A1

公开(公告)日：2015-05-14

申请号：US14601804

申请日：2015-01-21

申请人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Jenn Hwa Huang ,  Karen E. Moore

IPC分类号： H01L21/285

CPC分类号： H01L21/28581 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0615 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.

摘要翻译： 半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及 第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。 图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。

公开(公告)号：US20130157456A1

公开(公告)日：2013-06-20

申请号：US13764398

申请日：2013-02-11

申请人： Darrell G. Hill ,  Bruce M. Green

发明人： Darrell G. Hill ,  Bruce M. Green

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An electronic device having a conductive substrate via extending between a conductor on a rear face and a conductor over a front face of the substrate includes a multi-layered etch-stop beneath the front surface conductor. The etch-stop permits use of a single etchant to penetrate both the substrate and any overlying semiconductor and/or dielectric without attacking the overlying front surface conductor. This is especially important when the semiconductor and dielectric are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop is preferably a stack of N≧2 pairs of sub-layers, where a first sub-layer comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer comprises etch resistant material (e.g., Ni). In a further embodiment, where the device includes field effect transistors having feedback sensitive control gates, the etch-stop material is advantageously used to form gate shields.

摘要翻译： 具有通过在后表面上的导体与衬底的前表面之间的导体之间延伸的导电衬底的电子器件包括在前表面导体下方的多层蚀刻停止。 蚀刻停止允许使用单个蚀刻剂来穿透基板和任何上覆的半导体和/或电介质，而不会攻击上覆的前表面导体。 当半导体和电介质如此薄以至于在蚀刻期间达到这些区域时阻止改变蚀刻剂时，这尤其重要。 蚀刻停止优选地是N> = 2对子层的堆叠，其中第一子层包括减轻应力和/或粘附促进材料（例如，Ti），并且第二子层包括耐蚀刻材料 （例如Ni）。 在另一实施例中，其中器件包括具有反馈敏感控制栅极的场效应晶体管，蚀刻停止材料有利地用于形成栅极屏蔽。