公开(公告)号：US20130321184A1

公开(公告)日：2013-12-05

申请号：US13488544

申请日：2012-06-05

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/38

CPC classification number: H03M1/164 ,  H03M1/46

Abstract: A method for operating a SAR assisted pipelined ADC includes enabling a SAR ADC in a current stage circuit for converting an input analog voltage into a digital code during a first time interval, resetting an operational amplifier of an MDAC in the current stage circuit during the first time interval, maintaining the SAR ADC of the current stage circuit in an enabled state for outputting during a second time interval, and enabling the MDAC in the current stage circuit during the second time interval. The method also includes enabling the SAR ADC in the current stage circuit for sampling during a third time interval and connecting the output terminal of the MDAC in the current stage circuit to the input terminal of the next stage circuit during the third time interval. The first, second, and third time intervals are continuous and do not overlap each other.

Abstract translation: 一种用于操作SAR辅助流水线模数转换器的方法，包括：在当前级电路中启用SAR ADC，以便在第一时间间隔期间将输入模拟电压转换为数字代码，在第一时间段期间复位当前级电路中的MDAC的运算放大器 时间间隔，将当前级电路的SAR ADC保持在使能状态，以在第二时间间隔期间输出，并且在第二时间间隔期间启用当前级电路中的MDAC。 该方法还包括使得当前级电路中的SAR ADC在第三时间间隔期间进行采样，并且在第三时间间隔期间将当前级电路中的MDAC的输出端连接到下一级电路的输入端。 第一，第二和第三时间间隔是连续的，并且彼此不重叠。

公开(公告)号：US08390501B2

公开(公告)日：2013-03-05

申请号：US13096908

申请日：2011-04-28

Applicant: Soon-Jyh Chang ,  Guan-Ying Huang ,  Chun-Cheng Liu ,  Chung-Ming Huang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Guan-Ying Huang ,  Chun-Cheng Liu ,  Chung-Ming Huang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: H03M1/34

CPC classification number: H03M1/462 ,  H03M1/466

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.

Abstract translation: 公开了逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 第一和第二电容器DAC分别接收第一和第二输入信号。 第一粗略比较器将第一电容器DAC的输出与窗口参考电压进行比较，第二粗略比较器将第二电容器DAC的输出与窗口参考电压进行比较，精细比较器将第一电容器DAC的输出与 第二电容DAC的输出。 SAR控制器接收第一和第二粗略比较器的输出，以确定第一和第二电容器DAC的输出是否在由窗口参考电压确定的预测窗口内。 当第一电容器DAC和第二电容器DAC的输出被确定为在预测窗口内时，SAR控制器绕过至少一个SAR模数转换阶段。 SAR控制器解码第一和第二粗略比较器和精细比较器的输出，以获得SAR ADC的转换输出。

公开(公告)号：US08299952B1

公开(公告)日：2012-10-30

申请号：US13093649

申请日：2011-04-25

Applicant: Jin-Fu Lin ,  Chia-Hsuan Huang

Inventor： Jin-Fu Lin ,  Chia-Hsuan Huang

IPC: H03M1/12

CPC classification number: H03K5/00 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45986 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/442

Abstract: A switched-capacitor circuit which comprises a first sampling capacitor, a second sampling capacitor, an op-amp, a third capacitor, and a fourth capacitor is provided. The first sampling capacitor is disposed to sample an input signal in a sampling phase. The second sampling capacitor is disposed to sample the input signal in the sampling phase. Wherein, in a first amplify phase, the third capacitor stores an offset voltage of the op-amp, the fourth capacitor stores the electric charges which are flowed from the first sampling capacitor and the second sampling capacitor, and in a second amplify phase, the fourth capacitor gives the stored electric charges back to the first sampling capacitor and the second sampling capacitor.

Abstract translation: 提供了包括第一采样电容器，第二采样电容器，运算放大器，第三电容器和第四电容器的开关电容器电路。 第一采样电容器设置成在采样阶段对输入信号进行采样。 第二采样电容器设置成在采样阶段对输入信号进行采样。 其中，在第一放大相位中，第三电容器存储运算放大器的偏移电压，第四电容器存储从第一采样电容器和第二采样电容器流出的电荷，并且在第二放大相位中， 第四电容器将存储的电荷返回到第一采样电容器和第二采样电容器。

公开(公告)号：US08217819B2

公开(公告)日：2012-07-10

申请号：US12941510

申请日：2010-11-08

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin

IPC: H03M1/66

CPC classification number: H03M1/0653 ,  H03M1/806

Abstract: The present invention is directed to a multiplying digital-to-analog converter (MDAC) and its method. First ends of capacitors are electrically coupled to an inverting input node of an amplifier, wherein two of the capacitors are alternatively configured as a feedback capacitor. Each capacitor is composed of at least two sub-capacitors. Second ends of capacitors are electrically coupled to an input signal via a number of sampling switches, and the second ends of the capacitors are electrically coupled to DAC voltages respectively via a number of amplifying switches. A sorting circuit is configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.

Abstract translation: 本发明涉及一种乘法数模转换器（MDAC）及其方法。 电容器的第一端电耦合到放大器的反相输入节点，其中两个电容器被配置为反馈电容器。 每个电容器由至少两个子电容器组成。 电容器的第二端通过多个采样开关电耦合到输入信号，并且电容器的第二端分别经由多个放大开关电耦合到DAC电压。 排序电路被配置为对子电容器进行排序，其中分选的子电容器然后被配对，使得子电容器之间的失配的变化被平均化。

公开(公告)号：US08570206B1

公开(公告)日：2013-10-29

申请号：US13455515

申请日：2012-04-25

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/34

CPC classification number: H03M1/144

Abstract: A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.

Abstract translation: 主数字模拟转换器（DAC）接收至少一个输入并产生经调整的输入。 SAR单元基于接收经调整的输入的比较单元的比较输出产生用于控制主DAC的代码。 参考发生器在产生的代码的控制下产生至少一个参考电压，然后在每个相应周期中转发给比较单元，用于定义每个周期的搜索范围，其中后者的参考电压的绝对值 周期小于前一周期的参考电压，使得后一周期的搜索范围小于前一周期的搜索范围，并且所有周期的搜索范围以基极电压为中心。

公开(公告)号：US08502713B1

公开(公告)日：2013-08-06

申请号：US13470701

申请日：2012-05-14

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/06

CPC classification number: H03M1/0607 ,  H03M1/0695 ,  H03M1/167 ,  H03M1/44

Abstract: A method for correcting a voltage offset influence of a pipelined analog to digital converter is disclosed, in which the method generates a first stage code and a first output voltage according to a first input voltage, generates a second stage code according to the first output voltage, generates a check code according to the first output voltage, determines a first correction code by referring to the first stage code and the check code, and corrects the first stage code with the first correction code when the first stage code is different from the first correction code.

Abstract translation: 公开了一种用于校正流水线模数转换器的电压偏移影响的方法，其中该方法根据第一输入电压产生第一级代码和第一输出电压，根据第一输出电压产生第二级代码 根据第一输出电压生成检查码，通过参照第一级代码和校验码确定第一校正码，并且当第一级代码与第一级代码不同于第一级代码时，用第一校正码校正第一级代码 校正码。

公开(公告)号：US08400343B1

公开(公告)日：2013-03-19

申请号：US13276287

申请日：2011-10-18

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/38

CPC classification number: H03M1/14 ,  H03M1/164 ,  H03M1/468

Abstract: A stage of a pipeline analog-to-digital converter (ADC) is provided according to embodiments of the present invention. The stage of the present invention has double-amplifier architecture and uses level-shifting technique to generate a residue of the stage. The amplifiers of the stage are implemented in two different split paths, thereby to generate a relatively coarse amplification result and a relative fine amplification result. The relatively coarse amplification result is used to level-shift the output level of the amplifier. As a result, the stage of the present invention can have a correct residual by using amplifiers of moderate quality.

Abstract translation: 根据本发明的实施例提供了一个流水线模数转换器（ADC）的级。 本发明的阶段具有双放大器架构，并且使用电平转换技术来产生阶段的残留。 级的放大器以两个不同的分离路径实现，从而产生相对粗略的放大结果和相对精细的放大结果。 相对粗略的放大结果用于对放大器的输出电平进行电平移位。 结果，通过使用中等质量的放大器，本发明的阶段可以具有正确的残差。

公开(公告)号：US08344930B2

公开(公告)日：2013-01-01

申请号：US13101127

申请日：2011-05-04

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/12

CPC classification number: H03M1/002 ,  H03M1/468

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

Abstract translation: 逐次逼近寄存器（SAR）模数转换器（ADC）包括第一电容器阵列，第一输入电容器，第一开关模块，第二电容器阵列，第二输入电容器，第二开关模块，比较器和 一个SAR控制器。 SAR ADC在采样相位和放大阶段多次运行，以对输入信号进行放大操作和ADC操作，以生成数字输出数据。 此外，由于SAR ADC具有放大功能和ADC功能，所以使用SAR ADC的电路不需要额外的有源PGA，电路的功耗也会降低。

公开(公告)号：US20120280846A1

公开(公告)日：2012-11-08

申请号：US13101127

申请日：2011-05-04

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/12

CPC classification number: H03M1/002 ,  H03M1/468

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

Abstract translation: 逐次逼近寄存器（SAR）模数转换器（ADC）包括第一电容器阵列，第一输入电容器，第一开关模块，第二电容器阵列，第二输入电容器，第二开关模块，比较器和 一个SAR控制器。 SAR ADC在采样相位和放大阶段多次运行，以对输入信号进行放大操作和ADC操作，以生成数字输出数据。 此外，由于SAR ADC具有放大功能和ADC功能，所以使用SAR ADC的电路不需要额外的有源PGA，电路的功耗也会降低。

公开(公告)号：US07924204B2

公开(公告)日：2011-04-12

申请号：US12247186

申请日：2008-10-07

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: H03M1/38

CPC classification number: H03M1/1225 ,  H03M1/0695 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

Abstract: An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.

Abstract translation: 公开了一种用于流水线ADC或循环ADC的模数转换器（ADC）。 ADC包括串联连接的至少一对两个级，两级具有不同的分辨率。 放大器由一对两个级共享，使得两个级以交错方式操作。 因此，这种阶段分辨率可扩展的运算放大器共享技术适用于流水线ADC或循环ADC，这大大降低了功耗并提高了运行速度。